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HT68FU50 数据表(PDF) 23 Page - Holtek Semiconductor Inc |
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HT68FU50 数据表(HTML) 23 Page - Holtek Semiconductor Inc |
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23 / 244 page ![]() Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fLIRC System Clock (LIRC) 5V Ta=25 °C -10% 32 +10% kHz 2.2V~ 5.5V Ta= -40°C~+85°C -50% 32 +60% kHz fTIMER Timer Input Pin Frequency ¾¾ ¾ ¾ 1 fSYS tRES External Reset Low Pulse Width ¾¾ 1 ¾¾ ms tINT Interrupt Pulse Width ¾¾ 1 ¾¾ tSYS tLVR Low Voltage Width to Reset ¾¾ 120 240 480 ms tLVD Low Voltage Width to Interrupt ¾¾ 20 45 90 ms tLVDS LVDO stable time ¾¾ 15 ¾¾ ms tBGS VBG Turn on Stable Time ¾¾ 200 ¾¾ ms tEERD EEPROM Read Time ¾¾ ¾ 45 90 ms tEEWR EEPROM Write Time ¾¾ ¾ 24 ms tSST System Start-up Timer Period (Wake-up from HALT) ¾ fSYS=HXT or LXT ¾ 1024 ¾ tSYS fSYS=ERC or HIRC ¾ 15~16 ¾ fSYS=LIRC OSC ¾ 1~2 ¾ Note: 1. tSYS=1/fSYS 2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1 mF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Comparator Electrical Characteristics Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VCMP Comparator Operating Voltage ¾¾ 2.2 ¾ 5.5 V ICMP Comparator Operating Current 3V ¾¾ 37 56 mA 5V ¾¾ 130 200 mA VCMPOS Comparator Input Offset Voltage ¾¾ -10 ¾ 10 mV VHYS Hysteresis Width ¾¾ 20 40 60 mV VCM Comparator Common Mode Voltage Range ¾¾ VSS ¾ VDD -1.4V V AOL Comparator Open Loop Gain ¾¾ 60 80 ¾ dB tPD Comparator Response Time ¾ With 100mV overdrive (Note) ¾ 370 560 ns Note: Measured with comparator one input pin at VCM =(VDD -1.4)/2 while the other pin input transition from VSS to (VCM +100mV) or from VDD to (VCM -100mV). HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Rev. 1.50 23 March 15, 2011 Ta=25 °C |
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