HT68FU50 datasheet(93/244 Pages) HOLTEK

93 / 244 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

March 15, 2011

These three bits are used to setup the value on the internal CCRP 3-bit register, which are then

compared with the internal counter's highest three bits. The result of this comparison can be

selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to

zero ensures that a compare match with the CCRP values will reset the internal counter. As the

CCRP bits are only compared with the highest three counter bits, the compare values exist in 128

clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at

its maximum value.

· TMnC1 Register

Bit

76543210

Name

TnM1

TnM0

TnIO1

TnIO0

TnOC

TnPOL

TnDPX

TnCCLR

R/W

POR

00000000

Bit 7~6

TnM1~TnM0: Select TMn Operating Mode

00: Compare Match Output Mode

01: Undefined

10: PWM Mode

11: Timer/Counter Mode

These bits setup the required operating mode for the TM. To ensure reliable operation the TM

should be switched off before any changes are made to the TnM1 and TnM0 bits. In the

Timer/Counter Mode, the TM output pin control must be disabled.

Bit 5~4

TnIO1~TnIO0: Select TPn_0, TPn_1 output function

Compare Match Output Mode

00: No change

01: Output low

10: Output high

11: Toggle output

PWM Mode

00: PWM output inactive state

01: PWM output active state

10: PWM output

11: Undefined

Timer/counter Mode

unused

These two bits are used to determine how the TM output pin changes state when a certain

condition is reached. The function that these bits select depends upon in which mode the TM is

running.

In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output

pin changes state when a compare match occurs from the Comparator A. The TM output pin can

be setup to switch high, switch low or to toggle its present state when a compare match occurs

from the Comparator A. When the bits are both zero, then no change will take place on the

output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1

the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin

when a compare match occurs. After the TM output pin changes state it can be reset to its initial

level by changing the level of the TnON bit from low to high.

In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state

when a certain compare match condition occurs. The PWM output function is modified by

changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only

after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and

TnIO0 bits are changed when the TM is running

Bit 3

TnOC: TPn_0, TPn_1 Output control bit

Compare Match Output Mode

0: Initial low

1: Initial high

PWM Mode

0: Active low

1: Active high

HT68FU50 数据表(PDF) 93 Page - Holtek Semiconductor Inc

HT68FU50 数据表(HTML) 93 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载