HT68FU50 datasheet(78/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

March 15, 2011

I/O Pin Structures

The accompanying diagrams illustrate the internal

structures of some generic I/O pin types. As the exact

logical construction of the I/O pin will differ from these

drawings, they are supplied as a guide only to assist

with the functional understanding of the I/O pins. The

wide range of pin-shared structures does not permit all

types to be shown.

Programming Considerations

Within the user program, one of the first things to con-

sider is port initialisation. After a reset, all of the I/O data

and port control registers will be set high. This means

that all I/O pins will default to an input state, the level of

which depends on the other connected circuitry and

whether pull-high selections have been chosen. If the

port control registers, PAC~PGC, are then programmed

to setup some pins as outputs, these output pins will

have an initial high output value unless the associated

port data registers, PA~PG, are first programmed. Se-

lecting which pins are inputs and which are outputs can

be achieved byte-wide by loading the correct values into

the appropriate port control register or by programming

individual bits in the port control register using the

²SET

[m].i

² and ²CLR [m].i² instructions. Note that when using

these bit control instructions, a read-modify-write opera-

tion takes place. The microcontroller must first read in

the data on the entire port, modify it to the required new

bit values and then rewrite this data back to the output

ports.

Port A has the additional capability of providing wake-up

functions. When the device is in the SLEEP or IDLE

Mode, various methods are available to wake the device

up. One of these is a high to low transition of any of the

Port A pins. Single or multiple pins on Port A can be

setup to have this function.

V D D

W a k e - u p S e l e c t

S y s t e m W a k e - u p

R e a d D a t a R e g i s t e r

C K

C o n t r o l B i t

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

I / O p i n

P A o n l y

W e a k

P u l l - u p

P u l l - H i g h

R e g i s t e r

S e l e c t

Generic Input/Output Structure

HT68FU50 数据表(PDF) 78 Page - Holtek Semiconductor Inc

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