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HT68FU50 数据表(PDF) 65 Page - Holtek Semiconductor Inc |
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HT68FU50 数据表(HTML) 65 Page - Holtek Semiconductor Inc |
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65 / 244 page ![]() HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 HT68FU30/HT68FU40/HT68FU50/HT68FU60 Rev. 1.50 65 March 15, 2011 Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PG. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output opera- tion, all the data is latched and remains unchanged until the output latch is rewritten. · I/O Register List ¨ HT68F20 Register Name Bit 76543210 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU ¾¾ D5 D4 D3 D2 D1 D0 PB ¾¾ D5 D4 D3 D2 D1 D0 PBC ¾¾ D5 D4 D3 D2 D1 D0 PCPU ¾¾¾¾ D3 D2 D1 D0 PC ¾¾¾¾ D3 D2 D1 D0 PCC ¾¾¾¾ D3 D2 D1 D0 ¨ HT68F30 Register Name Bit 76543210 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU ¾¾ D5 D4 D3 D2 D1 D0 PB ¾¾ D5 D4 D3 D2 D1 D0 PBC ¾¾ D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 |
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