HT68FU50 datasheet(98/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

March 15, 2011

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter cleared

by CCRA

Pause Resume

Counter Stop if

TnON bit low

Counter Reset when

TnON returns high

TnDPX = 1; TnM [1:0] = 10

PWMDutyCycle

set by CCRP

PWM resumes

operation

Output controlled by

other pin-shared function

Output Inverts

when TnPOL = 1

PWM Period

set by CCRA

TM O/P Pin

(TnOC=0)

PWM Mode -- TnDPX = 1

Note:

1. Here TnDPX=1-- Counter cleared by CCRA

2. A counter clear sets the PWM Period

3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

· CTM, PWM Mode, Edge-aligned Mode, T0DPX=0

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

128

256

384

512

640

768

896

1024

Duty

CCRA

If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128,

The CTM PWM output frequency = (fSYS/4)/512=fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%.

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty

is 100%.

· CTM, PWM Mode, Edge-aligned Mode, T0DPX=1

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

CCRA

Duty

128

256

384

512

640

768

896

1024

The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cy-

cle is defined by the CCRP register value.

HT68FU50 数据表(PDF) 98 Page - Holtek Semiconductor Inc

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HT68FU50 数据表(PDF) 98 Page - Holtek Semiconductor Inc

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