HT68FU50 datasheet(101/244 Pages) HOLTEK

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

101

March 15, 2011

Bit 3

T1ON: TM1 Counter On/Off Control

0: Off

1: On

This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to

run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting

and turn off the TM which will reduce its power consumption. When the bit changes state from

low to high the internal counter value will be reset to zero, however when the bit changes from

high to low, the internal counter will retain its residual value until the bit returns high again.

If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial

condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.

Bit 2~0

T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7

Comparator P Match Period

000: 1024 TM1 clocks

001: 128 TM1 clocks

010: 256 TM1 clocks

011: 384 TM1 clocks

100: 512 TM1 clocks

101: 640 TM1 clocks

110: 768 TM1 clocks

111: 896 TM1 clocks

These three bits are used to setup the value on the internal CCRP 3-bit register, which are then

compared with the internal counter's highest three bits. The result of this comparison can be

selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to

zero ensures that a compare match with the CCRP values will reset the internal counter. As the

CCRP bits are only compared with the highest three counter bits, the compare values exist in 128

clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at

its maximum value.

¨ TM1C1 Register - 10-bit STM

Bit

76543210

Name

T1M1

T1M0

T1IO1

T1IO0

T1OC

T1POL

T1DPX

T1CCLR

R/W

POR

00000000

Bit 7~6

T1M1~T1M0: Select TM1 Operating Mode

00: Compare Match Output Mode

01: Capture Input Mode

10: PWM Mode or Single Pulse Output Mode

11: Timer/Counter Mode

These bits setup the required operating mode for the TM. To ensure reliable operation the TM

should be switched off before any changes are made to the T1M1 and T1M0 bits. In the

Timer/Counter Mode, the TM output pin control must be disabled.

Bit 5~4

T1IO1~T1IO0: Select TP1_0, TP1_1 output function

Compare Match Output Mode

00: No change

01: Output low

10: Output high

11: Toggle output

PWM Mode/Single Pulse Output Mode

00: PWM output inactive state

01: PWM output active state

10: PWM output

11: Single pulse output

Capture Input Mode

00: Input capture at rising edge of TP1_0, TP1_1

01: Input capture at falling edge of TP1_0, TP1_1

10: Input capture at falling/rising edge of TP1_0, TP1_1

11: Input capture disabled

Timer/counter Mode:

Unused

HT68FU50 数据表(PDF) 101 Page - Holtek Semiconductor Inc

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