HT68FU50 datasheet(197/244 Pages) HOLTEK

197 / 244 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.50

197

March 15, 2011

· Address detect mode

Setting the Address Detect function enable control bit,

ADDEN, in the UCR2 register, enables this special

function. If this bit is set to

²1², then an additional qual-

ifier will be placed on the generation of a Receiver

Data Available interrupt, which is requested by the

RXIF flag. If the ADDEN bit is equal to

²1², then when

the data is available, an interrupt will only be gener-

ated, if the highest received bit has a high value. Note

that the related interrupt enable control bit and the

EMI bit of the microcontroller must also be enabled for

correct interrupt generation. The highest address bit is

the 9th bit if the bit BNO=1 or the 8th bit if the bit

BNO=0. If the highest bit is high, then the received

word will be defined as an address rather than data. A

Data Available interrupt will be generated every time

the last bit of the received word is set. If the ADDEN bit

is equal to

²0², then a Receive Data Available interrupt

will be generated each time the RXIF flag is set, irre-

spective of the data last but status. The address de-

tect and parity functions are mutually exclusive

functions. Therefore if the address detect function is

enabled, then to ensure correct operation, the parity

function should be disabled by resetting the parity

function enable bit PREN to zero.

ADDEN

Bit 9 if BNO=1,

Bit 8 if BNO=0

UART Interrupt

Generated

ADDEN Bit Function

UART Module Power-down and Wake-up

The MCU and UART Module are powered down inde-

pendently of each other. The method of powering down

the MCU is covered in the previous MCU section of the

datasheet. The UART Module must be powered down

before the MCU is powered down. This is implemented

by first clearing the UARTEN bit in the UCR1 register to

disable the UART Module circuitry after which the SCS

internal line can be set high to disable the SPI interface

circuits. When the UART and SPI interfaces are pow-

ered down, the SCK and CLKI clock sources to the

UART module will be disabled. The UART Module can

be powered up by the MCU by first clearing the SCS line

to zero and then setting the UARTEN bit. If the UART

circuits is powered down while a transmission is still in

progress, then the transmission will be terminated and

the external TX transmit pin will be forced to a logic high

level. In a similar way, if the UART circuits is powered

down while receiving data, then the reception of data will

likewise be terminated. When the UART circuits is pow-

ered down, note that the USR, UCR1, UCR2, UCR3,

transmit and receive registers, as well as the BRG regis-

ter will not be affected.

The UART Module contains a receiver RX pin wake-up

function, which is enabled or disabled by the WAKE bit

in the UCR2 register. If this bit, along with the UART en-

able bit named UARTEN, the receiver enable bit named

RXEN and the receiver interrupt enable bit named RIE,

are all set before the MCU and UART module are is

powered down, then a falling edge on the RX pin will

wake up the MCU from its power down condition. Note

U S R R e g i s t e r

T r a n s m i t t e r E m p t y

F l a g T X I F

T r a n s m i t t e r I d l e

F l a g T I D L E

R e c e i v e r D a t a

A v a i l a b l e R X I F

R e c e i v e r O v e r r u n

F l a g O E R R

R X 7 i f B N O = 0

R X 8 i f B N O = 1

A D D E N

R X P i n

W a k e - u p

W A K E

U C R 2 R e g i s t e r

T E I E

T I I E

R I E

U C R 2 R e g i s t e r

O R

T o M C U P I N T i n t e r r u p t i n p u t

I N T

UART Interrupt Structure

HT68FU50 数据表(PDF) 197 Page - Holtek Semiconductor Inc

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