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ADAU1373BCBZ-R7 数据表(PDF) 266 Page - Analog Devices |
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ADAU1373BCBZ-R7 数据表(HTML) 266 Page - Analog Devices |
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266 / 296 page ![]() ADAU1373 Rev. 0 | Page 266 of 296 Bits Bit Name Settings Description Reset Access 3 DMICCLKDRV Driving Ability of DMIC CLOCK. Driving ability setting for digital microphone clock. 0x1 RW 0 Low 1 High (default) 2 CDRV Driving Ability of Audio Interface C. Driving ability setting of Audio Interface C. 0x1 RW 0 Low 1 High (default) 1 BDRV Driving Ability of Audio Interface B. Driving ability setting of Audio Interface B. 0x1 RW 0 Low 1 High (default) 0 ADRV Driving Ability of Audio Interface A. Driving ability setting of Audio Interface A. 0x1 RW 0 Low 1 High (default) PAD_CTRL2 REGISTER Address: 0xEA, Reset: 0x0F, Name: PAD_CTRL2 Pin Drive Capability Control Register Table 238. Bit Descriptions for PAD_CTRL2 Bits Bit Name Settings Description Reset Access [7:4] RESERVED Reserved. 0x0 RW 3 GPIO4DRV Driving Ability of GPIO4. Driving ability setting for GPIO4. 0x1 RW 0 Low 1 High (default) 2 GPIO3DRV Driving Ability of GPIO3. Driving ability setting for GPIO3. 0x1 RW 0 Low 1 High (default) 1 GPIO2DRV Driving Ability of GPIO2. Driving ability setting for GPIO2. 0x1 RW 0 Low 1 High (default) 0 GPIO1DRV Driving Ability of GPIO1. Driving ability setting for GPIO1. 0x1 RW 0 Low 1 High (default) |
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