WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port

Rev. 1.4

May 2011

Page 10 of 32

CONTROL/STATUS REGISTER

Accessing the unique features of WM72016 is accomplished through the Control/Status register in F-RAM

non-volatile memory.

The register is located at physical address 0x016 or USER memory address 0x002.

The Control/Status word register is organized as shown in Table 3 below. Care should be exercised when

writing the Control/Status register word if it is to remain unlocked.

LCK

PLCK

RFU

BW

EN

BLKSIZ

WRP

WRP

EN

ALCK

AINC

Figure 10. Control/Status Register

Table 3: Control/Status Word Register

Bit

Mnemonic

Function

Initial

Value

15

LOCK

Memory locking of this register.

LOCK

PERMALOCK

DESCRIPTION

0

0

Register unlocked

0

1

Register permanently unlocked

1

0

Register writeable only from the

SECURED state

1

1

Register permanently locked

0

14

PERMALOCK

0

13

RFU

Reserved for future use

0

12

RFU

Reserved for future use

0

11

RFU

Reserved for future use

0

10

RFU

Reserved for future use

0

9

RFU

Reserved for future use

0

8

RFU

Reserved for future use

0

7

BLKWREN

Enables use of the custom command BLOCKWRITE.

1

6

BLKSIZ[2]

USER memory block size.

BLKSIZ[2:0]

# words

BLKSIZ[2:0]

# words

000

1

100

16

001

2

101

32

010

4

110

64

011

8

111

128

1

5

BLKSIZ[1]

1

4

BLKSIZ[0]

0

3

WRPSTAT

Indicates if the Working Stored Address has wrapped.

Logic State

Description

0

Wrapping has not occurred

1

Wrapping has occurred at least once

0

2

WRPEN

Enables wrapping of the Working Stored Address when it reaches the

top of logical memory.

Logic State

Description

0

DISABLE memory wrapping

1

ENABLE memory wrapping.

0

1

AUTOLOCK

Enable Automatic Locking of all user memory between the start of USER

memory and the Working Stored Address register.

Logic State

Description

0

Auto-lock DISABLED

1

Auto-lock ENABLED

0

0

AUTOINCR

Enable the Working Stored Address word to Auto-Increment when

performing an unaddressed write cycle.

Logic State

Description

0

DISABLE auto-increment of stored address register

1

ENABLE auto-increment of stored address register

0