WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port

Rev. 1.4

May 2011

Page 19 of 32

DUAL SERIAL PERIPHERAL INTERFACE (DSPI)

The WM72016 employs a dual serial peripheral interface (DSPI) bus providing a serial communication port to

a host microcontroller for the purpose of directly reading and writing memory. The interface uses four pins as

shown in Table 7.

Table 7: DSPI Interface

Signal Name

Direction

Description

CS

INPUT/OUTPUT

Chip Select

D1

INPUT/OUTPUT

Data bit 1

D0

INPUT/OUTPUT

Data bit 0

CLK

INPUT

Clock

A single DSPI access cycle is composed of a 16-bit instruction word and a 16-bit data word as shown in Figure

20. A DSPI read/write cycle is initiated by asserting CS high followed by 16 clock cycles. The host drives the

first set of 8 clock cycles to write 2 data bytes comprising an instruction word – the second set of 8 clock

cycles are required for the 16-bit data word. Command and data bits are interleaved across two DSPI data

signals in such a manner that odd numbered bits are driven on one data signal while even numbered bits are

driven on the other data signal as shown in section DSPI Serial Port Timing. This results in a 16-bit word

transfer on the D0 and D1 signals every 8 clock cycles.

INSTR_WORD

INSTR_WORD

DATA_WORD

DATA_WORD

CS

CLK

D0

D1

Figure 20. DSPI Cycle

WRITE CYCLES

DSPI write cycles are detailed in the DSPI Serial Port Timing section. The host microcontroller drives all four

DSPI signals for the duration of the cycle. The WM72016 uses the rising edge of CLK to shift in the 2 data

bits presented on the D1 and D0 signals. The host microcontroller shall obey the timing constraints detailed in

Table 10.

The host microcontroller asserts the 2 data bits prior to the rising edge of CLK.

The host

microcontroller shifts the instruction word with the first set of 8 CLK cycles and shifts the data word on the

second set of 8 CLK cycles. The write cycle is terminated by clearing the CS signal.

READ CYCLES

SPI read cycles are detailed in the DSPI Serial Port Timing section. The host microcontroller shall transmit the

instruction word in the same manner as done for DSPI write cycles. The WM72016 uses the rising edge of

CLK to shift in the 2 data bits presented on the D1 and D0 signals. Once the instruction word has been

completely transmitted and the CLK signal has been cleared to a logic zero, the host shall tri-state the D1 and

D0 signals allowing the WM72016 to drive the data bits for the remainder of the read cycle. The WM72016

shall shift a pair of data bits on D1 and D0 on the rising edge of CLK – the host shall use the falling edge of

CLK to capture the data pair into its shift register. The host shall transmit a total of 8 CLK cycles to receive

the entire data word, after which it clears the CS to a logic zero to terminate the read cycle.

The syntax of the instruction word is detailed in Table 8.