WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port

Rev. 1.4

May 2011

Page 21 of 32

d14

d12

d10

d8

d6

d4

d2

d0

OP4 OP2 OP0

a8

a6

a4

a2

a0

d15

d13

d11

d9

d7

d5

d3

d1

WR

OP3 OP1

a9

a7

a5

a3

a1

CS

D0

D1

CLK

Figure 21. DSPI Write Cycle Detail

Note: In the event of a simultaneous memory access, the RFID request will take priority over the

secondary DSPI serial interface.

MICROCONTROLLER INTERRUPTS

The WM72016 is capable of generating interrupts initiated by a RFID interrogator to a microcontroller on the

serial port. Interrupt generation provides a mechanism to alert a host microcontroller that a RFID interrogator

is present and to take control of the memory with no possibility of interruption from the RFID interface.

During an interrupt, all RFID commands are disregarded until an INTEND DSPI command is received to

terminate the interrupt and return control back to the RFID interface.

An interrupt is generated from the WM72016 to the host by writing two standard Gen2 write cycles to USER

memory addresses 0x004 and 0x005. The XOR operation of the two data words written to the two respective

addresses must equal 0x1234. As with all Gen2 write commands, the WM72016 must be in the OPEN or

SECURED state prior to executing the write command sequence. Should the WM72016 RFID have a non-

zero ACCESS password, the device must be transitioned to the SECURED state by correctly accessing the tag

with the device‟s ACCESS password. The RFID interrogator then transmits two cover-coded WRITE

commands to USER memory addresses 0x004 and 0x005 whose two data words when XORed together result

in a value of 0x1234. A correct sequence of the WRITE commands will result in the WM72016 asserting an

interrupt by driving the DSPI CS high.

Upon detection of a high state on the CS signal, the host

microcontroller drives two clock cycles on the DSPI CLK to acknowledge and clear the WM72016 interrupt.

The host microcontroller now has full and uninhibited access to the WM72016 memory. Any attempted access

by a RFID interrogator during this period will be disregarded until one of two conditions has occurred:



The host microcontroller has released control of the WM72016 memory by writing an instruction with

the INTEND opcode, or



The WM72016 has been power-cycled.

The entire interrupt generation sequence is shown in Figure 22. Note that the values x1200 and x0034 shown

in Figure 22 are shown for illustration purposes only – any two values whose XOR operation results in a value

of x1234 will generate a DSPI interrupt.

The host microcontroller releases its control of the WM72016

memory by writing an instruction with an INTEND opcode refer to Table 9. The contents of the DSPI write

data word payload that follows the instruction word are ignored but must be present to constitute a valid DSPI

command.

NOTE: Should the outcome of two write cycles to USER memory locations 0x004 and 0x005 result in a XOR

value that is not 0x1234, the interrupt mechanism will be disabled until the WM72016 has been power-cycled.

In this case, the two memory locations may be used as standard USER memory, however any future use of

these memory locations may potentially generate an unintended interrupt – as such, it is not recommended to

use these memory locations as part of the standard USER memory bank.