WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port

Rev. 1.4

May 2011

Page 28 of 32

CIRCUIT EXAMPLE

The WM72016 may be implemented in a manner similar to that shown below.

CLK

D1

D0

CS

Vddr

ANT+

ANT-

VDDR_EXT

µP

GND

I/O

I/O

I/O

I/O

Bus termination

may be required

Vddraw

Matching

network

NOTES:

1.

RF performance of WM72016 is heavily dependent on matching impedance on the antenna port ANT+/-.

2.

External voltage VDDR_EXT may be applied to Vddraw to externally power the WM72016.

VDDR_EXT must comply with specifications given in the DC Characteristics of this datasheet.

3.

In some cases, additional bus termination may be required on the WM72016 end of the DSPI serial bus.

This is dependent on a number of factors, including bus length, bus impedance, connectors, processor

drive voltage, I/O port drive strength, and I/O slew rate. Excessive ringing on the bus may generate

voltages beyond specifications causing unpredictable performance characteristics.