ADE7816 datasheet(43/48 Pages) AD

43 / 48 page

Data Sheet

ADE7816

Rev. 0| Page 43 of 48

Table 26. ACCMODE Register (Address 0xE701)

Bits

Bit Name

Default

Value

Description

REVRPSEL

0x0

0: the sign of the reactive power is monitored on the A, B, and C channels.

1: the sign of the reactive power is monitored on the D, E, and F channels.

REVAPSEL

0x0

0: the sign of the active power is monitored on the A, B, and C channels.

1: the sign of the active power is monitored on the D, E, and F channels.

[5:4]

Reserved

0x00

These bits should be ignored and not modified.

00: signed accumulation for all reactive power measurements.

01: reserved.

10: reserved.

[3:2]

VARACC[1:0]

0x00

11: reserved.

[1:0]

WATTACC[1:0]

0x00

00: signed accumulation for all active power measurements.

01: reserved.

10: reserved.

11: reserved.

Table 27. LCYCMODE Register (Address 0xE702)

Bits

Bit Name

Default

Value

Description

Reserved

0x0

Reserved. This bit does not control any functionality.

RSTREAD

0x1

Enables read-with-reset for all energy registers. Note that this bit has no function in line cycle

accumulation mode and should be set to 0 when this mode is in use.

[5:4]

Reserved

0x0

These bits should be ignored.

ZX_SEL

0x0

Enables the voltage channel zero-crossing counter for line cycle accumulation mode.

Reserved

0x0

These bits should be ignored.

LVAR

0x0

Enables the reactive energy line cycle accumulation mode.

LWATT

0x0

Enables the active energy line cycle accumulation mode.

Table 28. HSDC_CFG Register (Address 0xE706)

Bits

Bit Name

Default

Value

Description

[7:6]

Reserved

0x00

These bits should be ignored.

HSAPOL

0x0

0: SS/HSA output pin is active low (default).

1: SS/HSA output pin is active high.

[4:3]

HXFER[1:0]

0x00

00 = reserved.

01 = HSDC transmits current and voltage waveform data.

10 = reserved.

11 = reserved.

HGAP

0x0

0: no gap is introduced between packages (default).

1: a gap of seven HCLK cycles is introduced between packages.

HSIZE

0x0

0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first (default).

1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.

HCLK

0x0

0: HSCLK = 8 MHz (default).

1: HSCLK = 4 MHz.

Table 29. CONFIG2 Register (Address 0xEC01)

Bits

Bit Name

Default

Value

Description

[7:2]

Reserved

0x0

These bits should be ignored.

I2C_LOCK

0x0

Serial port lock.

EXTREFEN

0x0

Set to 1 to use with an external reference.

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