ADE7816 datasheet(31/48 Pages) AD

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Data Sheet

ADE7816

Rev. 0 | Page 31 of 48

OUTPUTS

This section describes the outputs from the ADE7816.

INTERRUPTS

The ADE7816 has two interrupt pins, IRQ0 and IRQ1. Each pin is

managed by a 32-bit interrupt mask register, MASK0 and MASK1

(Address 0xE50A and Address 0xE50B), respectively. To enable

an interrupt, a bit in the MASKx register must be set to 1. To

disable an interrupt, the bit must be cleared to 0. Two 32-bit

status registers, STATUS0 and STATUS1 (Address 0xE502 and

Address 0xE503, respectively), are associated with the interrupts.

When an interrupt event occurs in the

, the corre-

sponding flag in the interrupt status register is set to a Logic 1

(see

and

). If the mask bit for this interrupt in

the interrupt mask register is Logic 1, the

ADE7816

Table 30

Table 31

IRQx logic output goes

active low. The flag bits in the interrupt status register are set,

irrespective of the state of the mask bits. To determine the source

of the interrupt, the microcontroller must perform a read of the

corresponding STATUSx register and identify which bit is set to 1.

To erase the flag in the status register, write back to the STATUSx

status register is read and the source of the interrupt is identified.

Then, the status register is written back, with no changes, to

clear the status flag to 0. The IRQx pin remains low until the

status flag is cancelled.

By default, all interrupts are disabled, with the exception of

the RSTDONE interrupt. This interrupt can never be masked

(disabled) and, therefore, Bit 15 (RSTDONE) in the MASK1

goes low, and Bit 15 (RSTDONE) in the STATUS1 register is set

to 1 whenever a power-up or a hardware/software reset process

ends. To cancel the RSTDONE status flag, the STATUS1 register

nust be written with Bit 15 (RSTDONE) set to 1.

COMMUNICATION

Serial Interface Selection

After reset, the HSDC port is always disabled. Choose between the

I2C and SPI ports by manipulating the SS/HSA pin after power-up

or after a hardware reset. If the SS/HSA pin is held high, the

uses the I2C port until a new hardware reset is executed.

If the

ADE7816

SS/HSA pin is toggled high to low three times after power-up

or after a hardware reset, the

uses the SPI port until a

new hardware reset is executed. This manipulation of the

ADE7816

SS/HSA

pin can be accomplished in two ways. The first option is to use

the SS/HSA pin of the master device (that is, the microcontroller)

as a regular I/O pin and toggle it three times. The second option is

to execute three SPI write operations to a location in the address

space that is not allocated to a specific

Address 0xEBFF, where 8-bit writes can be executed).

ADE7816

These writes allow the SS/HSA pin to toggle three times. See the

SPI Write Operation section for details on the write protocol

that is involved.

After the serial port choice is completed, it must be locked.

If I2C is the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2

on, the ADE7816 ignores spurious toggling of the SS/HSA pin,

and an eventual switch to use of the SPI port is no longer possible.

If the SPI is the active serial port, any write to the CONFIG2

longer possible.

The functionality of the ADE7816 is accessible via several on-chip

registers. The contents of these registers can be updated or read,

using either the I2C or SPI interfaces. The HSDC port provides the

instantaneous values of the voltages and current channels.

I2C-Compatible Interface

The ADE7816 supports a fully licensed I2C interface. The I2C

interface is implemented as a full hardware slave. SDA is the data

I/O pin, and SCL is the serial clock. These two pins are shared with

the MOSI and SCLK pins, respectively, of the on-chip SPI interface.

The maximum serial clock frequency supported by this interface is

400 kHz.

The SDA and SCL pins are used for data transfer and are con-

figured in a wire-AND’ed format that allows arbitration in a

multimaster system.

The transfer sequence of an I2C system consists of a master device

initiating a transfer by generating a start condition while the bus

is idle. The master transmits the address of the slave device and the

direction of the data transfer in the initial address transfer. If the

slave acknowledges, the data transfer is initiated. This continues

until the master issues a stop condition and the bus becomes idle.

I2C Write Operation

The write operation, using the I2C interface of the ADE7816,

initiated when the master generates a start condition, consists

of one byte representing the address of the ADE7816, followed

by the 16-bit address of the target register and by the value of

the register.

The most significant seven bits of the address byte constitute

the address of the ADE7816, which is 0111000b. Bit 0 of the

address byte is a read/write bit. Because this is a write operation,

it must be cleared to 0; therefore, the first byte of the write

operation is 0x70. After every byte is received, the

generates an acknowledge. The register can be 8, 16, or 32 bits

in length. After the last bit of the register is transmitted and the

acknowledges the transfer, the master generates a stop

condition. The addresses and the register content are sent with

the most significant bit first. See

for details of the I2C

write operation.

ADE7816

Figure 39

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