ADE7816 datasheet(29/48 Pages) AD

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Data Sheet

ADE7816

Rev. 0 | Page 29 of 48

This method of determining the power factor does not take into

account the effect of any harmonics.

When Bits[10:9] (ANGLESEL) of the COMPMODE register are

set to 10b, the time delays (angles) between current channels are

measured. Table 10 shows the current channel-to-channel delay

measure-ments that are available.

Table 10. Available Channel-to-Channel Measurements

(ANGLESEL = 10b)

Channel-to-Channel Measurements

CHANNEL_SEL

(COMPMODE[14])

ANGLE0

ANGLE1

ANGLE2

A to B

A to C

B to C

A to E

D to F

E to F

The ANGLE0 (Address 0xE601), ANGLE1 (Address 0xE602), and

ANGLE2 (Address 0xE603) registers are 16-bit, unsigned registers

with 1 LSB corresponding to 3.90625 μs (256 kHz clock), which

corresponds to a resolution of 0.0703° (360° × 50 Hz/256 kHz)

for 50 Hz systems and 0.0843° (360° × 60 Hz/256 kHz) for 60 Hz

systems.

PERIOD MEASUREMENT

The ADE7816 provides the period measurement of the line in

the voltage channel. The period register (Address 0xE607) is

a 16-bit, unsigned register that updates every line period. Due

to internal filtering, a settling time of 30 ms to 40 ms is associ-

ated with this measurement.

The period measurement has a resolution of 3.90625 μs/LSB

(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)

when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)

when the line frequency is 60 Hz. The value of the period register

for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and

for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The

length of the register enables the measurement of line frequencies

that are as low as 3.9 Hz (256 kHz/216). The period register is stable

at ±1 LSB when the line is established, and the measurement

does not change.

The following expressions can be used to compute the line period

and frequency, using the period register:

[ ]

(17)

sec

256

PERIOD[15:

]

[

256

PERIOD[15:

VOLTAGE SAG DETECTION

The ADE7816 includes a sag detection feature that warns the

user when the absolute value of the line voltage falls below the

programmable threshold for a programmable number of line

cycles. This feature can provide an early warning signal that the

line voltage is dropping out. The voltage sag feature is controlled

by two registers: SAGCYC (Address 0xE704) and SAGLVL

(Address 0xE509). These registers control the sag period and

the sag voltage threshold, respectively.

Sag detection is disabled by default and can be enabled by writing

a nonzero value to both the SAGCYC and SAGLVL registers. If

either register is set to 0, the sag feature is disabled. If a voltage

sag condition occurs, the sag bit (Bit 16) in the STATUS1 register

(Address 0xE503) is set to 1.

SETTING THE SAGCYC REGISTER

The 8-bit, unsigned SAGCYC register contains the programmable

sag period. The sag period is the number of half line cycles below

which the voltage channel must remain before a sag condition

occurs. Each LSB of the SAGCYC register corresponds to a half

line cycle period. The SAGCYC register holds a maximum

value of 255.

At 50 Hz, the maximum sag cycle time is 2.55 seconds.

⎟

⎠

⎞

⎜

⎝

⎛

÷ 2

× 255 = 2.55 sec

At 60 Hz, the maximum sag cycle time is 2.125 seconds.

⎟

⎠

⎞

⎜

⎝

⎛

÷ 2

× 255 = 2.125 sec

If the SAGCYC value is modified after the feature is enabled,

the new SAGCYC period is effective immediately. Therefore, it

is possible for a sag event to be caused by a combination of sag

cycle periods. To prevent any overlap, the SAGLVL register should

be reset to 0 to effectively disable the feature before the new cycle

value is written to the SAGCYC register.

SETTING THE SAGLVL REGISTER

The content of the 24-bit SAGLVL register is compared to the

absolute value of the output from the HPF. Writing 5,928,256

(0x5A7540) to the SAGLVL register sets the sag detection level

at full scale. This results in the sag event triggering continuously.

Writing 0x00 or 0x01 puts the sag detection level at 0; therefore,

the sag event is never triggered.

VOLTAGE SAG INTERRUPT

The ADE7816 includes an interrupt that is associated with the

voltage sag detection feature. If this interrupt is enabled, a voltage

sag event causes the external IRQ1 pin to go low. This interrupt

is disabled by default and can be enabled by setting the sag bit

(Bit 16) in the MASK1 register, Address 0xE50B (see the

section).

Interrupts

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