ADE7816 datasheet(33/48 Pages) AD

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Data Sheet

ADE7816

Rev. 0 | Page 33 of 48

The SS logic input is the chip select input. This input is used

when multiple devices share the serial bus. Drive the SS input

low for the entire data transfer operation. Bringing SS high

during a data transfer operation aborts the transfer and places

the serial bus in a high impedance state. A new transfer can

then be initiated by returning the SS logic input to low. However,

because aborting a data transfer before completion leaves the

accessed register in a state that cannot be guaranteed, the value of a

The protocol is similar to the protocol used with the I2C interface.

SPI Read Operation

The read operation, using the SPI interface, initiates when the

master sets the SS/HSA pin low and begins sending one byte,

representing the address of the

, on the MOSI line. The

master sets data on the MOSI line starting with the first high-to-

low transition of SCLK. The

SPI samples data on the

low-to-high transitions of SCLK. The most significant seven bits

of the address byte can have any value, but, as good programming

practice, they should be different from 0111000b, the seven bits

used in the I2C protocol. Bit 0 (read/

ADE7816

write) of the address byte must

be set to 1 for a read operation. Next, the master sends the 16-bit

address of the register to be read. After the

receives the

last address bit of the register on a low-to-high transition of SCLK,

it begins to transmit its contents on the MISO line when the next

SCLK high-to-low transition occurs; thus, the master can sample

the data on a low-to-high SCLK transition. After the master

receives the last bit, it sets the

ADE7816

SS and SCLK lines high, and the

communication ends. The data lines, MOSI and MISO, go into

a high impedance state (see

Figure 41

SPI Write Operation

The write operation, using the SPI interface, initiates when the

master sets the SS/HSA pin low and begins sending one byte,

representing the address of the

, on the MOSI line. The

master sets data on the MOSI line, starting with the first high-to-

low transition of SCLK. The SPI samples data on the low-to-high

transitions of SCLK. The most significant seven bits of the address

byte can have any value, but, as a good programming practice,

they should be different from 0111000b, the seven bits that are used

in the I2C protocol. Bit 0 (read/

ADE7816

write) of the address byte must be 0

for a write operation. Next, the master sends the 16-bit address

of the register that is written and the 32-, 16-, or 8-bit value of that

mitted, the master sets the SS and SCLK lines high at the end of

the SCLK cycle and the communication ends. The data lines, MOSI

and MISO, go into a high impedance state (see

Figure 42

15 14

SCLK

MOSI

MISO

31 30

1 0

0 0 0

Figure 41. SPI Read Operation of a 32-Bit Register

15 14

SCLK

MOSI

10 31 30

1 0

000 0

ADDRESS

Figure 42. SPI Write Operation of a 32-Bit Register

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