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ADE7816 数据表(PDF) 26 Page - Analog Devices |
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ADE7816 数据表(HTML) 26 Page - Analog Devices |
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26 / 48 page ![]() ADE7816 Data Sheet Rev. 0 | Page 26 of 48 POWER QUALITY FEATURES This section describes the power quality features that are available in the ADE7816. SELECTING A CURRENT CHANNEL GROUP When using the power quality features on the current channels, the group of channels to be monitored must be selected. Bit 14 (CHANNEL_SEL) of the COMPMODE register (Address 0xE60E) can be used to make this selection. To select the A, B, and C current channels for the current channel power quality measurements, CHANNEL_SEL must be set to 0 (default). To select the D, E, and F current channels for the current channel power quality measurements, CHANNEL_SEL must be set to 1. If all channels require monitoring, the monitoring must be done in series by modifying the CHANNEL_SEL bit after data is obtained. The settling time of each power quality measurement is provided in the section that pertains to each power quality feature. INSTANTANEOUS WAVEFORMS The ADE7816 provides access to the current and voltage channel waveform data. This information allows the instantaneous data to be analyzed in more detail, including reconstruction of the current and voltage input for harmonic analyses. These measure- ments are available from a set of 24-bit, signed registers. The voltage channel has a dedicated register, VWV (Address 0xE510), whereas the current channels share three registers: IAWV/IDWV (Address 0xE50C), IBWV/IEWV (Address 0xE50D), and ICWV/ IFWV (Address 0xE50E). A group of current channels (A, B, C or D, E, F) must be selected by Bit 14 (CHANNEL_SEL) of the COMPMODE register (see the Selecting a Current Channel Group section). All measurements are updated at a rate of 8 kHz. The ADE7816 provides an interrupt status bit, DREADY (Bit 17 of the STATUS0 register, Address 0xE502), that is triggered at a rate of 8 kHz, allowing measurements to be synchronized with the instanta- neous update signal rate. The instantaneous update signal can also be configured to trigger an interrupt on the external pin by setting the DREADY bit (Bit 17) in the MASK0 register (Address 0xE50A). With the specified full-scale analog input signal of 0.5 V, the expected reading on the current and voltage waveform register is approximately ±5,989,256 (dec). The instantaneous waveforms have no additional settling time, and, therefore, if the CHANNEL_SEL bit is modified to change the group of current channels being measured, the new result is available in 125 μs (8 kHz). ZERO-CROSSING DETECTION Zero-Crossing Detection The ADE7816 has a zero-crossing (ZX) detection circuit on the voltage and current channels. Zero-crossing detection allows measurements to be synchronized to the frequency of the incoming waveforms. The zero-crossing events are filtered internally by an LPF. The LPF is intended to eliminate all harmonics of 50 Hz and 60 Hz systems, and to help identify the zero-crossing events on the fundamental components of both current and voltage channels. The digital filter has a pole at 80 Hz and is clocked at 256 kHz. As a result, there is a phase lag between the analog input signal and the output of the LPF. The error in ZX detection is 0.0703° for 50 Hz systems and 0.0843° for 60 Hz systems. The phase lag response of the LPF results in a time delay of approximately 31.4° or 1.74 ms (at 50 Hz) between its input and output. The overall delay between the zero crossing on the analog inputs and the ZX detection that is obtained after LPF1 is about 39.6° or 2.2 ms (at 50 Hz). Figure 33 shows how the zero-crossing signal is detected. To provide further protection from noise, input signals to the voltage channel with an amplitude of <10% of full scale do not generate zero-crossing events at all. The ZX detection circuit of the current channels is active for all input signals, independent of their amplitudes. IxGAIN OR VGAIN REFERENCE HPF PGA ADC IA, IB, IC, ID, IE, IF, OR V ZX DETECTION LPF_ZX IA, IB, IC, ID, IE, IF, OR V 39.6° OR 2.2ms @ 50Hz 1 0.855 0V ZX ZX ZX ZX LPF_ZX OUTPUT Figure 33. Zero-Crossing Detection |
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