ADE7816 datasheet(17/48 Pages) AD

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Data Sheet

ADE7816

Rev. 0 | Page 17 of 48

INPUTS

The following section provides details on the ADE7816 input

connections that are required for correct functionality.

POWER AND GROUND

VDD and AGND, DGND

To power the ADE7816, a 3.3 V dc input voltage should be

provided between the VDD pin and the AGND and DGND pins.

In addition, the PULL_HIGH and PULL_LOW pins must be

connected to 3.3 V and AGND, respectively. This configuration

is shown in Figure 24.

0.22µF

4.7µF

PULL_HIGH

PULL_LOW

0.22µF

4.7µF

3.3V

Figure 24. Applying Power to the ADE7816

The ADE7816 contains an on-chip power supply monitor that

supervises the power supply (VDD). When the voltage applied

to the VDD pin is below 2 V ± 10%, the chip is in an inactive

state. After VDD crosses the 2 V ± 10% threshold, the power

supply monitor keeps the ADE7816 in an inactive state for an

additional 26 ms. This time delay allows VDD to reach the

minimum specified operating voltage of 3.3 V − 10%. When

the minimum specified operating voltage is met and the

PULL_HIGH and PULL_LOW pins are tied to VDD and

AGND, respectively, the internal circuitry is enabled. This

process is accomplished in approximately 40 ms.

When the start-up sequence is complete and the ADE7816 is

ready to receive communication from a microcontroller, the

RSTDONE flag is set in the STATUS1 register (Address 0xE503).

An external interrupt is triggered on the IRQ1 pin. The RSTDONE

interrupt is enabled by default and cannot be disabled; therefore,

an external interrupt always occurs at the end of a power-up

procedure or hardware or software reset.

It is highly recommended that the RSTDONE interrupt be used

by the microcontroller to gate the first communication with the

ADE7816. If the interrupt is not used, a timeout can be imple-

mented. However, because the start-up sequence can vary from

part to part and over temperature, a timeout of a least 100 ms is

recommended. The RSTDONE interrupt provides the most time-

efficient way of monitoring the completion of the ADE7816

start-up sequence.

The AVDD and DVDD output pins provide access to the on-

chip analog and digital LDOs. When the ADE7816 is fully

powered up, these pins are at 2.5 V. If the internal reference is

being used, the REFIN/OUT pin outputs 1.2 V (see the Reference

Circuit section).

When the start-up sequence is complete, all registers are at their

default value, and the I2C port is the active serial port. Commu-

nication with the ADE7816 can begin. See the Communication

section for more details.

To start the energy and rms computations, the internal DSP

must be powered up after all configuration registers are set to

their desired values. The DSP is started by setting the run register

(Address 0xE228) to 0x0001. See the Starting and Stopping the

DSP section for more information.

REFERENCE CIRCUIT

REFIN/OUT

The nominal reference voltage at the REFIN/OUT pin is 1.2 V ±

0.075%. The REFIN/OUT pin can be overdriven by an external 1.2 V

reference source. If Bit 0 (EXTREFEN) in the CONFIG2 register

(Address 0xEC01) is cleared to 0 (the default value), the ADE7816

uses the internal voltage reference. If Bit 0 is set to 1, the external

voltage reference is used.

The voltage of the ADE7816 internal reference drifts slightly with

temperature; see the Specifications section for the temperature

coefficient specification (in ppm/°C). The value of the temperature

drift varies from part to part. Because the reference is used for

all ADCs, any x% drift in the reference results in a 2x% deviation

of the meter accuracy.

RESET

Hardware Reset

To initiate a hardware reset of the ADE7816, the RESET pin must

be pulled low for at least 10 μs. After the RESET pin returns high,

all registers return to their default values. The

signals the

end of the transition period by triggering the

ADE7816

IRQ1 interrupt pin

low and setting Bit 15 (RSTDONE) in the STATUS1 register to 1.

This bit is set to 0 during the transition period and changes to 1

when the transition ends.

Software Reset Functionality

Bit 7 (SWRST) in the CONFIG register (Address 0xE618) manages

the software reset functionality in the ADE7816. The default value

of this bit is 0. If Bit 7 is set to 1, the ADE7816 enters the software

reset state. In this state, all internal registers are set to their default

values, with the exception of the CONFIG2 register, which retains

its existing value. In addition, the choice of which serial port is in

use (I2C or SPI) remains unchanged if the lock-in procedure was

executed previously (see the

Communication section for details).

When the software reset ends, Bit 7 (SWRST) in the CONFIG

(RSTDONE) in the STATUS1 register is set to 1. RSTDONE is

set to 0 during the transition period and changes to 1 when the

transition ends.

It is recommended that all meters be designed to have both

software and hardware reset capability.

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