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ADP1853ACPZ-R7 数据表(PDF) 7 Page - Analog Devices |
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ADP1853ACPZ-R7 数据表(HTML) 7 Page - Analog Devices |
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7 / 28 page  Data Sheet ADP1853 Rev. 0 | Page 7 of 28 SIMPLIFIED BLOCK DIAGRAM Figure 2. BST PGND + – + – + – + – FB OV_TH UV_TH PGOOD CURRENT SENSE AMPLIFIER DH DL ILIM SW VREF = 0.6V + + – ERROR AMPLIFIER FB COMP SS PWM COMPARATOR SLOPE COMPENSATION AND RAMP GENERATOR CURRENT-LIMIT CONTROL RAMP 50µA OV + TRK CS GAIN DRIVER LOGIC CONTROL AND STATE MACHINE OVER_LIM PULSE SKIP OVER_LIM LDO LOGIC EN VIN UVLO OSCILLATOR FREQ SYNC REF VCCO OV UV 0.6V THERMAL SHUTDOWN AGND CS FAULT OV LOGIC OVER_LIM OV EN EN_SW LOGIC UV 3kΩ 0.9V DCM *0 (ZERO) GAIN IS FOR VOLTAGE MODE WITH RAMP FROM 0.7V TO 2.2V. ZERO CROSS DETECT 12.5kΩ AV = 0,* 3, 6, 12 VCCO CLK EN_SW 1MΩ – + CLKOUT VCCO VCCO VCCO VCCO SLAVE SL_TH FB SLAVE 0.6V 6.5µA |
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