ADP1853ACPZ-R7 datasheet(14/28 Pages) AD

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ADP1853

Data Sheet

Rev. 0 | Page 14 of 28

SYNCHRONOUS RECTIFIER AND DEAD TIME

In the ADP1853, the antishoot-through circuit monitors the

DH to SW and DL to PGND voltages and adjusts the low-side

and high-side drivers to ensure break-before-make switching

that prevents cross-conduction or shoot-through between

the high-side and low-side MOSFETs. This break-before-make

switching is known as dead time, which is not fixed and

depends on how fast the MOSFETs are turned on and off. In

a typical application circuit that uses medium sized MOSFETs

with an input capacitance of approximately 3 nF, the typical

dead time is approximately 25 ns. When small and fast

MOSFETs with fast diode recovery times are used, the dead

time can be as low as 13 ns.

INPUT UNDERVOLTAGE LOCKOUT

When the bias input voltage at the VIN pin is less than the

undervoltage lockout (UVLO) threshold of 2.6 V typical, the

switch drivers stay inactive. If EN is high, the controller starts

switching and the VIN pin voltage exceeds the UVLO

threshold.

INTERNAL LINEAR REGULATOR

The internal linear regulator is a low dropout (LDO) VCCO.

VCCO powers up the internal control circuitry and provides

power for the gate drivers. It is guaranteed to have more than

200 mA of output current capability, which is sufficient to

handle the gate driver requirements of typical logic threshold

MOSFETs driven at up to 1.5 MHz. VCCO is always active

and cannot be shut down by the EN signal; however, the over-

temperature protection event disables the LDO together with

the controller. Bypass VCCO to AGND with a 1 µF or greater

capacitor.

Because the LDO supplies the gate driver current, the output of

VCCO is subject to sharp transient currents as the drivers

switch and the boost capacitors recharge during each switching

cycle. The LDO has been optimized to handle these transients

without overload faults. Due to the gate drive loading, using the

VCCO output for other external auxiliary system loads is not

recommended.

The LDO includes a current limit that is well above the

expected maximum gate driver load. This current limit also

includes a short-circuit foldback to further limit the VCCO

current in the event of a short-circuit fault.

For an input voltage of less than 5.5 V, it is recommended to

bypass the LDO by connecting VIN to VCCO, as shown in

Figure 20, thus eliminating the dropout voltage. However, if

the input range is 4 V to 7 V, the LDO cannot be bypassed by

shorting VIN to VCCO because the 7 V input has exceeded the

maximum voltage rating of the VCCO pin. In this case, use the

LDO to drive the internal drivers, but keep in mind that there is

a dropout when VIN is less than 5 V.

Figure 20. Configuration for VIN < 5.5 V

OVERVOLAGE PROTECTION

The ADP1853 has a built-in circuit for detecting output over-

voltage at the FB node. When the FB voltage, VFB, rises above

the overvoltage threshold, the high-side N-channel MOSFET

(NMOSFET) is turned off, and the low-side NMOSFET is

turned on until the VFB drops below the undervoltage threshold.

This action is known as the crowbar overvoltage protection.

If the overvoltage condition is not removed, the controller

maintains the feedback voltage between the overvoltage and

undervoltage thresholds, and the output is regulated to within

typically +8% and −8% of the regulation voltage. During an

overvoltage event, the SS node discharges toward zero through

an internal 3 kΩ pull-down resistor. When the voltage at FB

drops below the undervoltage threshold, the soft start sequence

restarts. Figure 21 shows the overvoltage protection scheme in

action in PSM.

Figure 21. Overvoltage Protection in PSM

POWER GOOD

The PGOOD pin is an open-drain NMOSFET with an internal

12.5 kΩ pull-up resistor connected between PGOOD and

VCCO. PGOOD is internally pulled up to VCCO during

normal operation and is active low when tripped. When the

feedback voltage, VFB, rises above the overvoltage threshold

or drops below the undervoltage threshold, the PGOOD output

is pulled to ground after a delay of 12 µs. The overvoltage or

undervoltage condition must exist for more than 10 µs for

PGOOD to become active. The PGOOD output also becomes

active if a thermal overload condition is detected.

ADP1853

VIN

VIN = 2.75V TO 5.5V

VCCO

CH1 20V

CH2 5V

CH3 1V

CH4 10V

M100µs

A CH1

10V

PGOOD

VOUT = 1.8V SHORTED TO 2V SOURCE

VIN

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