Data Sheet

ADP1853

Rev. 0 | Page 9 of 28

Pin No.

Mnemonic

Description

17

PGOOD

Power Good. The open-drain power good indicator logic output with an internal 12.5 kΩ resistor is connected

between PGOOD and VCCO. PGOOD is pulled to ground when the output is outside the regulation window. An

external pull-up resistor is not required. If the controller is configured as a slave in the interleaved dual-phase

application by tying the FB pin high to VCCO, the pulse skip mode is enabled by driving the PGOOD pin low

externally in cases when the master is in pulse skip mode at light loads. Otherwise, if the master is configured to

forced PWM operation, PGOOD of the slave controller must be connected to the PGOOD of the master.

18

RAMP

Programmable Current Setting for Slope Compensation. Connect a resistor from RAMP to V

is 0.2 V during operation. This pin is high impedance when the channel is disabled.

19

FREQ

Internal Oscillator Frequency, f

resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz or tie FREQ to VCCO for

600 kHz operating frequency.

20

TRK

Tracking Input. Connect TRK to VCCO if tracking is not used.

EPAD

Exposed Pad. Connect the bottom of the exposed pad to the system AGND plane.