ADP5040ACPZ-1-R7 datasheet(26/40 Pages) AD

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ADP5040

Data Sheet

Rev. 0 | Page 26 of 40

Thermal Protection

In the event that the junction temperature rises above 150°C,

the thermal shutdown circuit turns off the buck and the LDOs.

Extreme junction temperatures can be the result of high current

operation, poor circuit board design, or high ambient temperature.

A 20°C hysteresis is included in the thermal shutdown circuit so

that when thermal shutdown occurs, the buck and the LDOs do

not return to normal operation until the on-chip temperature

drops below 130°C. When coming out of thermal shutdown, all

regulators start with soft start control.

Undervoltage Lockout

To protect against battery discharge, undervoltage lockout

(UVLO) circuitry is integrated in the ADP5040. If the input

voltage on AVIN drops below a typical 2.15 V UVLO threshold,

all channels shut down. In the buck channel, both the power

switch and the synchronous rectifier turn off. When the voltage

on AVIN rises above the UVLO threshold, the part is enabled

once more.

Alternatively, the user can select device models with a UVLO

set at a higher level, suitable for 5 V applications. For these

models, the device reaches the turn-off threshold when the

input supply drops to 3.65 V typical.

Enable/Shutdown

The ADP5040 has individual control pins for each regulator.

A logic level high applied to the ENx pin activates a regulator,

whereas a logic level low turns off a regulator.

Active Pull-Down

The ADP5040 can be purchased with the active pull-down

option enabled. The pull-down resistors are connected between

each regulator output and AGND. The pull-downs are enabled,

when the regulators are turned off. The typical value of the pull-

down resistor is 600 Ω for the LDOs and 85 Ω for the buck.

BUCK SECTION

The buck uses a fixed frequency and high speed current mode

architecture. The buck operates with an input voltage of 2.3 V

to 5.5 V.

The buck output voltage is set though external resistor dividers,

as shown in Figure 102. VOUT1 must be connected to the

output capacitor. VFB1 is internally set to 0.5 V. The output

voltage can be set from 0.8 V to 3.8 V.

BUCK

VOUT1

VIN1

FB1

AGND

10µF

L1 – 1µH

Figure 102. Buck External Output Voltage Setting

Control Scheme

The buck operates with a fixed frequency, current mode PWM

control architecture at medium to high loads for high efficiency,

but operation shifts to a power save mode (PSM) control

scheme at light loads to lower the regulation power losses.

When operating in fixed frequency PWM mode, the duty cycle

of the integrated switches is adjusted and regulates the output

voltage. When operating in PSM at light loads, the output

voltage is controlled in a hysteretic manner, with higher output

voltage ripple. During part of this time, the converter is able to

stop switching and enters an idle mode, which improves

conversion efficiency.

PWM Mode

In PWM mode, the buck operates at a fixed frequency of 3 MHz,

set by an internal oscillator. At the start of each oscillator cycle,

the PFET switch is turned on, sending a positive voltage across

the inductor. Current in the inductor increases until the current

sense signal crosses the peak inductor current threshold that

turns off the PFET switch and turns on the NFET synchronous

rectifier. This sends a negative voltage across the inductor,

causing the inductor current to decrease. The synchronous

rectifier stays on for the rest of the cycle. The buck regulates the

output voltage by adjusting the peak inductor current threshold.

Power Save Mode (PSM)

The buck smoothly transitions to PSM operation when the load

current decreases below the PSM current threshold. When the

buck enters power save mode, an offset is introduced in the

PWM regulation level, which makes the output voltage rise.

When the output voltage reaches a level that is approximately

1.5% above the PWM regulation level, PWM operation is

turned off. At this point, both power switches are off, and the

buck enters an idle mode. The output capacitor discharges until

the output voltage falls to the PWM regulation voltage, at which

point the device drives the inductor to make the output voltage

rise again to the upper threshold. This process is repeated while

the load current is below the PSM current threshold.

ADP5040ACPZ-1-R7 数据表(PDF) 26 Page - Analog Devices

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