数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADP5040ACPZ-1-R7 数据表(PDF) 34 Page - Analog Devices

部件名 ADP5040ACPZ-1-R7
功能描述  Micro PMU with 1.2 A Buck Regulator
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5040ACPZ-1-R7 数据表(HTML) 34 Page - Analog Devices

Back Button ADP5040ACPZ-1-R7 Datasheet HTML 30Page - Analog Devices ADP5040ACPZ-1-R7 Datasheet HTML 31Page - Analog Devices ADP5040ACPZ-1-R7 Datasheet HTML 32Page - Analog Devices ADP5040ACPZ-1-R7 Datasheet HTML 33Page - Analog Devices ADP5040ACPZ-1-R7 Datasheet HTML 34Page - Analog Devices ADP5040ACPZ-1-R7 Datasheet HTML 35Page - Analog Devices ADP5040ACPZ-1-R7 Datasheet HTML 36Page - Analog Devices ADP5040ACPZ-1-R7 Datasheet HTML 37Page - Analog Devices ADP5040ACPZ-1-R7 Datasheet HTML 38Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 34 / 40 page
background image
ADP5040
Data Sheet
Rev. 0 | Page 34 of 40
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5040 performance, causing electro-
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
•
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
•
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
•
Maximize the size of ground metal on the component side
to help with thermal dissipation.
•
Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
SUGGESTED LAYOUT
See Figure 109 for an example layout.
NC
NC
NC
AGND
2
VOUT3
VOUT1
VOUT2
P P L
P P L
P P L
G P L
G P L
G P L
G P L
G P L
G P L
P P L
P P L
TOP LAYER
VIAS LEGEND:
PPL = POWER PLANE (+4V)
GPL = GROUND PLANE
2ND LAYER
MODE
EN
L1 – 1µH
0603
C5 – 4.7µF
10V/XR5 0603
C6 – 10µF
6.3V/XR5
0603
1.0
1.0
2.0
2.0
3.0
3.0
mm
mm
4.0
4.0
5.0
5.0
6.0
6.0
6.5
6.5
7.0
0.5
0.5
1.5
1.5
2.5
2.5
3.5
3.5
4.5
4.5
5.5
5.5
RFILT
30
Ω
0402
C3 – 1µF
10V/XR5
0402
C4– 2.2µF
6.3V/XR5
0402
C2 – 1µF
10V/XR5
0402
C5 – 2.2µF
6.3V/XR5
0402
AVIN
VIN
SW
PGND
EN1
ADP5040
Figure 109. Evaluation Board Layout



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com