ADP5040ACPZ-1-R7 datasheet(29/40 Pages) AD

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Data Sheet

ADP5040

Rev. 0 | Page 29 of 40

APPLICATIONS INFORMATION

BUCK EXTERNAL COMPONENT SELECTION

Trade-offs between performance parameters such as efficiency

and transient response are made by varying the choice of

external components in the applications circuit, as shown in

Figure 1.

Feedback Resistors

Referring to Figure 102, the total combined resistance for R1

and R2 is not to exceed 400 kΩ.

Inductor

The high switching frequency of the ADP5040 buck allows for

the selection of small chip inductors. For best performance, use

inductor values between 0.7 μH and 3.0 μH. Suggested inductors

are shown in Table 8.

The peak-to-peak inductor current ripple is calculated using

the following equation:

OUT

RIPPLE

−

)

(

where:

fSW is the switching frequency.

L is the inductor value.

The minimum dc current rating of the inductor must be greater

than the inductor peak current. The inductor peak current is

calculated using the following equation:

)

(

RIPPLE

MAX

LOAD

PEAK

Table 8. Suggested 1.0 μH Inductors

Vendor

Model

Dimensions

(mm)

ISAT

(mA)

DCR

(mΩ)

Murata

LQM2MPN1R0NG0B

2.0 × 1.6 × 0.9

1400

Murata

LQM18FN1R0M00B

3.2 × 2.5 × 1.5

2300

Tayo Yuden

CBC322ST1R0MR

3.2 × 2.5 × 2.5

2000

Coilcraft

XFL4020-102ME

4.0 × 4.0 × 2.1

5400

Coilcraft

XPL2010-102ML

1.9 × 2.0 × 1.0

1800

Toko

MDT2520-CN

2.5 × 2.0 × 1.2

1350

Inductor conduction losses are caused by the flow of current

through the inductor, which has an associated internal dc

resistance (DCR). Larger sized inductors have smaller DCR,

which may decrease inductor conduction losses. Inductor core

losses are related to the magnetic permeability of the core material.

Because the buck is high switching frequency dc-to-dc converter,

shielded ferrite core material is recommended for its low core

losses and low EMI.

Output Capacitor

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing the

capacitor value, it is also important to account for the loss of

capacitance due to output voltage dc bias.

Ceramic capacitors are manufactured with a variety of dielec-

trics, each with a different behavior over temperature and

applied voltage. Capacitors must have a dielectric adequate

to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. X5R or X7R

dielectrics with a voltage rating of 6.3 V or 10 V are highly

recommended for best performance. Y5V and Z5U dielectrics

are not recommended for use with any dc-to-dc converter

because of their poor temperature and dc bias characteristics.

The worst-case capacitance accounting for capacitor variation

over temperature, component tolerance, and voltage is calcu-

lated using the following equation:

CEFF = COUT × (1 − TEMPCO) × (1 − TOL)

where:

CEFF is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

COUT is 9.2481 μF at 1.8 V, as shown in Figure 105.

Substituting these values in the equation yields

CEFF = 9.24 μF × (1 − 0.15) × (1 − 0.1) = 7.07 μF

To guarantee the performance of the buck, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

DC BIAS VOLTAGE (V)

Figure 105. Typical Capacitor Performance

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using the following

equation:

(

)

OUT

RIPPLE

≈

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