SC667201MMG3 datasheet(21/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Introduction

triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock and one is clocked by the

crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is used to wake up the device from low power

stop mode.

The following features are implemented in the PIT:

•

5 independent timer channels

•

Each channel includes 32-bit wide down counter with automatic reload

•

4 channels clocked from system clock

•

1 channel clocked from crystal clock (wake-up timer)

•

Wake-up timer remains active when System STOP mode is entered; used to restart system clock after predefined

time-out period

•

Each channel optionally able to generate an interrupt request or a trigger event (to trigger eQADC queues) when timer

reaches zero

1.5.19.2

System timer module (STM)

The STM is designed to implement the software task monitor as defined by AUTOSAR1. It consists of a single 32-bit counter,

clocked by the system clock, and four independent timer comparators. These comparators produce a CPU interrupt when the

timer exceeds the programmed value.

The following features are implemented in the STM:

•

One 32-bit up counter with 8-bit prescaler

•

Four 32-bit compare channels

•

Independent interrupt source for each channel

•

Counter can be stopped in debug mode

1.5.20

Software watchdog timer (SWT)

The SWT is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core.

The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or

interrupt request when the correct software key is not written within the required time window.

The following features are implemented:

•

32-bit modulus counter

•

Clocked by system clock or crystal clock

•

Optional programmable watchdog window mode

•

Can optionally cause system reset or interrupt request on timeout

•

Reset by writing a software key to memory mapped register

•

Enabled out of reset

•

Configuration is protected by a software key or a write-once register

1.5.21

Cyclic redundancy check (CRC) module

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:

•

Support for CRC-16-CCITT (x25 protocol):

— x16 + x12 + x5 + 1

•

Support for CRC-32 (Ethernet protocol):

— x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

1. AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)

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