SC667201MMG3 datasheet(7/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Introduction

Table 2. MPC5642A series block summary

Block

Function

Boot assist module (BAM)

Block of read-only memory containing executable code that searches

for user-supplied boot code and, if none is found, executes the BAM

boot code resident in device ROM

Calibration bus interface

Transfers data across the crossbar switch to/from peripherals attached

to the calibration system connector

Controller area network (FlexCAN)

Supports the standard CAN communications protocol

Crossbar switch (XBAR)

Internal busmaster

Cyclic redundancy check (CRC)

CRC checksum generator

Deserial serial peripheral interface (DSPI)

Provides a synchronous serial interface for communication with

external devices

e200z4 core

Executes programs and interrupt handlers

Enhanced direct memory access (eDMA)

Performs complex data movements with minimal intervention from the

core.

Enhanced modular input-output system

(eMIOS)

Provides the functionality to generate or measure events

Enhanced queued analog-to-digital

converter (eQADC)

Provides accurate and fast conversions for a wide range of

applications

Enhanced serial communication interface

(eSCI)

Provides asynchronous serial communication capability with

peripheral devices and other microcontroller units

Enhanced time processor unit (eTPU2)

Second-generation co-processor processes real-time input events,

performs output waveform generation, and accesses shared data

without host intervention

Error Correction Status Module (ECSM)

The Error Correction Status Module supports a number of

miscellaneous control functions for the platform, and includes registers

for capturing information on platform memory errors if error-correcting

codes (ECC) are implemented

Flash memory

Provides storage for program code, constants, and variables

FlexRay

Provides high-speed distributed control for advanced automotive

applications

Frequency-modulated phase-locked loop

(FMPLL)

Generates high-speed system clocks and supports programmable

frequency modulation

Interrupt controller (INTC)

Provides priority-based preemptive scheduling of interrupt requests

JTAG controller

Provides the means to test chip functionality and connectivity while

remaining transparent to system logic when not in test mode

Memory protection unit (MPU)

Provides hardware access control for all memory references

generated

Nexus port controller (NPC)

Provides real-time development support capabilities in compliance

with the IEEE-ISTO 5001-2010 standard

Periodic interrupt timer (PIT)

Produces periodic interrupts and triggers

Reaction Module (REACM)

Works in conjunction with the eQADC and eTPU2 to increase system

performance by removing the CPU from the current control loop.

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