SC667201MMG3 datasheet(13/120 Pages) FREESCALE

13 / 120 page

MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Introduction

— Glitch detection on reset input

— Software controlled reset assertion

•

External interrupt

— Rising or falling edge event detection

— Programmable digital filter for glitch rejection

— Critical Interrupt request

— Non-Maskable Interrupt request

•GPIO

— Centralized control of I/O and bus pins

— Virtual GPIO via DSPI serialization (requires external deserialization device)

— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin

•

Internal multiplexing

— Allows serial and parallel chaining of DSPIs

— Allows flexible selection of eQADC trigger inputs

— Allows selection of interrupt requests between external pins and DSPI

— From a set of eTPU output channels, allows selection of source signals for decimation filter integrators

1.5.8

Flash memory

The MPC5642A provides 2 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used

to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash

array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array controller.

For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and

128-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches sequential lines of

data from the flash array into the buffers. Prefetch buffer hits allow no-wait responses.

The flash memory provides the following features:

•

Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword

reads are supported. Only aligned word and doubleword writes are supported.

•

Fetch Accelerator

— Architected to optimize the performance of the flash

— Configurable read buffering and line prefetch support

— 4-entry 128-bit wide line read buffer

— Prefetch controller

•

Hardware and software configurable read and write access protections on a per-master basis

•

Interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel

for pipelined flash array designs

•

Configurable access timing usable in a wide range of system frequencies

•

Multiple-mapping support and mapping-based block access timing (0–31 additional cycles) usable for emulation of

other memory types

•

Software programmable block program/erase restriction control

•

Erase of selected block(s)

•

Read page size of 128 bits (4 words)

•

ECC with single-bit correction, double-bit detection

•

Program page size of 128 bits (4 words) to accelerate programming

•

ECC single-bit error corrections are visible to software

•

Minimum program size is 2 consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC

SC667201MMG3 数据表(PDF) 13 Page - Freescale Semiconductor, Inc

SC667201MMG3 数据表(HTML) 13 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载