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SC667201MMG3 数据表(PDF) 95 Page - Freescale Semiconductor, Inc |
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SC667201MMG3 数据表(HTML) 95 Page - Freescale Semiconductor, Inc |
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95 / 120 page  MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 95 Electrical characteristics 3.17.4 Calibration bus interface timing Table 40. Calibration bus interface maximum operating frequency Port width Multiplexed mode Pin usage Max. operating frequency CAL_ADDR[12:15] CAL_ADDR[16:30] CAL_DATA[0:15] 16-bit Yes GPIO GPIO CAL_ADDR[12:30] CAL_DATA[0:15] 66 MHz1 1 Set SIU_ECCR[EBDF] to either divide by two or divide by four if the system frequency is greater than 66 MHz. 16-bit No CAL_ADDR[12:15] CAL_ADDR[16:30] CAL_DATA[0:15] 66 MHz1 32-bit Yes CAL_WE/BE[2:3] CAL_DATA[31] CAL_ADDR[16:30] CAL_DATA[16:30] CAL_ADDR[0:15] CAL_DATA[0:15] 66 MHz1 Table 41. Calibration bus operation timing1 # Symbol C Characteristic 66 MHz2 Unit Min Max 1TC CC P CLKOUT period3 15.2 — ns 2tCDC CC T CLKOUT duty cycle 45% 55% TC 3tCRT CC T CLKOUT rise time — 4 ns 4tCFT CC T CLKOUT fall time — 4 ns 5tCOH CC P CLKOUT Posedge to Output Signal Invalid or High Z (Hold Time) CAL_ADDR[12:30] CAL_CS[0], CAL_CS[2:3] CAL_DATA[0:15] CAL_OE CAL_RD_WR CAL_TS CAL_WE[0:3]/BE[0:3] 1.3 — ns 6tCOV CC P CLKOUT Posedge to Output Signal Valid (Output Delay) CAL_ADDR[12:30] CAL_CS[0], CAL_CS[2:3] CAL_DATA[0:15] CAL_OE CAL_RD_WR CAL_TS CAL_WE[0:3]/BE[0:3] —9 ns 7tCIS CC P Input Signal Valid to CLKOUT Posedge (Setup Time) DATA[0:31] 6.0 — ns 8tCIH CC P CLKOUT Posedge to Input Signal Invalid (Hold Time) DATA[0:31] 1.0 — ns 9tAPW CC P ALE Pulse Width 5 6.5 — ns 10 tAAI CC P ALE Negated to Address Invalid 5 1.56 —ns |
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