SC667201MMG3 datasheet(101/120 Pages) FREESCALE

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MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

101

Electrical characteristics

9tSUI

Data Setup Time for Inputs

Master (MTFE = 0)

VDDEH=4.75–5.25 V

—

VDDEH=3–3.6 V

—

DSlave

—

Master (MTFE = 1, CPHA = 0)12

8—

Master (MTFE = 1, CPHA = 1)

VDDEH=4.75–5.25 V

—

VDDEH=3–3.6 V

—

tHI

Data Hold Time for Inputs

Master (MTFE = 0)

4—

DSlave

—

Master (MTFE = 1, CPHA = 0)12

—

Master (MTFE = 1, CPHA = 1)

4—

tSUO

Data Valid (after SCK edge)

Master (MTFE = 0)

VDDEH=4.75–5.25 V

—

VDDEH=3–3.6 V

—

6.3

DSlave

VDDEH=4.75–5.25 V

—

VDDEH=3–3.6 V

—

25.7

Master (MTFE = 1, CPHA = 0)

—

Master (MTFE = 1, CPHA = 1)

VDDEH=4.75–5.25 V

—

VDDEH=3–3.6 V

—

6.3

tHO

Data Hold Time for Outputs

Master (MTFE = 0)

VDDEH=4.75–5.25 V

5—

VDDEH=3–3.6 V

6.3

—

DSlave

5.5

—

Master (MTFE = 1, CPHA = 0)

—

Master (MTFE = 1, CPHA = 1)

VDDEH=4.75–5.25 V

5—

VDDEH=3–3.6 V

6.3

—

1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type pad_msr. DSPI signals using pad type of

pad_ssr have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0 to 3.6 V, TA =TL to TH,

and CL = 50 pF with SRC = 0b11.

2 Data is verified at f

SYS = 102 MHz and 153 MHz (100 MHz and 150 MHz + 2% frequency modulation).

3 The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated

based on two MPC5642A devices communicating over a DSPI link.

4 The actual minimum SCK cycle time is limited by pad performance.

5 For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output,

maximum SCK frequency is 20 MHz. Appropriate clock division must be applied.

6 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

Table 46. DSPI timing1,2 (continued)

Symbol

Characteristic

Condition

Min.

Max.

Unit

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