MC34708 datasheet(39/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

MC34708

Functional Block Description

7.5.3.2

Silent Restart from PCUT Event

If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent

restart, so the system is reinitialized without alerting the user. This can be facilitated by setting the PCUTEXPB bit to “1” at booting

or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of PCUTEXPB

and the PCI bit. The PCUTEXPB is cleared to “0” when transitioning from PCUT to Off. If there was a PCUT interrupt and

PCUTEXPB is still “1”, then the state machine has not transitioned through Off, which confirms that the PCT timer has not expired

during the PCUT event (i.e., a successful power cut). In this case, a silent restart may be appropriate.

If PCUTEXPB is found to be “0” after the Cold Start where PCI is found to be “1”, then it is inferred that the PCT timer has expired

before power was reestablished, flagging an unsuccessful power cut or first power up, so the startup user greeting may be

desirable for playback.

7.5.3.3

Silent System Restart with WDI Event

A mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset,

but it is desired to make the reset a silent event so as to happen without end user awareness. The default response to WDI going

low is for the state machine to transition to the Off state (when WDIRESET = 0). However, if WDIRESET = 1, the state machine

will go to Cold Start without passing through Off mode (i.e., does not generate an OFFB signal).

A WDIRESET event will generate a maskable WDIRESETI interrupt and also increment the PCCOUNT counter. This function is

unrelated to PCUTs, but it shares the PCUT counter so that the number of silent system restarts can be limited by the

programmable PCMAXCNT counter.

When PCUT support is used, the software should set the PCUTEXPB bit to “1”. Since this bit resets with RTCPORB, it will not

be reset to “0” if a WDI falls and the state machine goes straight to the Cold Start state. Therefore, upon a restart, software can

discern a silent system restart if there is a WDIRESETI interrupt and PCUTEXPB = 1. The application may then determine that

an inconspicuous restart without fanfare may be more appropriate than launching into the welcoming routine.

A PCUT event does not trip the WDIRESETI bit.

Note that the system response to WDI is gated by the Watchdog timer—once the timer has expired, then the system will respond

as programmed by WDIRESET as described above.

7.5.3.4

Turn On Events

When in Off mode, the circuit can be powered on via a Turn On event. The Turn On events are listed by the following. To indicate

to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events.

Masking the interrupts related to the turn on events will not prevent the part to turn on except for the time of day alarm. If the part

was already on at the time of the turn on event, the interrupt is still generated.

• Power Button Press: PWRON1 or PWRON2 pulled low with corresponding interrupts and sense bits PWRON1I, or

PWRON2I and PWRON1S, or PWRON2S. A power on/off button is connected from PWRONx to ground. The PWRONx can

be hardware debounced through a programmable debouncer PWRONxDBNC [1:0] to avoid a response upon a very short (i.e.,

unintentional) key press. BP should be above UVDET to allow a power up. The PWRONxI interrupt is generated for both the

falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising

edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The

PWRONxI interrupt is cleared by software or when cycling through the Off mode.

Table 23. PWRONx Hardware Debounce Bit Settings(37)

Bits

State

Turn On

Debounce (ms)

Falling Edge INT

Debounce (ms)

Rising Edge INT

Debounce (ms)

PWRONxDBNC[1:0]

0.0

31.25

125

31.25

750

31.25

Notes

37.

The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin.

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