MC34708 datasheet(43/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

MC34708

Functional Block Description

mode. It will require the software to wake up occasionally to allow the mini-USB to detect if a device is attached by de-asserting

the STANDBY pin and waking up for a period to see if a device is attached and then re-asserting Standby, if a device has not

been detected. If a device has been detected then the software can bring up the appropriate application etc.

Note the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take

into account the programmed input polarity associated with each pin. For simplicity, Standby will generally be referred to as active

high throughout this document, but as defined in Table 29, active low operation can be accommodated. Finally, since STANDBY

pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin

level changes.

The state of the STANDBY pin only has influence in On mode, and are therefore it is ignored during start up and in the Watchdog

phase. This allows the system to power up without concern of the required Standby polarities since software can make

adjustments accordingly as soon as it is running.

A command to transition to one of the low power Off states (User Off or Memory Hold, initiated with USE-ROFFSPI=1) redefines

the power tree configuration based on SWxMODE programming, and has priority over Standby (which also influences the power

tree configuration).

7.5.3.8.2

Standby Delay

A provision to delay the Standby response is included. This allows the processor and peripherals, some time after a Standby

instruction has been received, to terminate processes to facilitate seamless Standby exiting and re-entrance into Normal

operating mode.

A programmable delay is provided to hold off the system response to a Standby event. When enabled (STBYDLY = 01, 10, or

11), STBYDLY will delay the STANDBY initiated response for the entire IC until the STBYDLY counter expires.

Note that this delay is applied only when going into Standby, and no delay is applied when coming out of Standby. Also, an

allowance should be accounted for synchronization of the asynchronous Standby event and the internal clocking edges (up to a

full 32 k cycle of additional delay).

Table 29. Standby Pin and Polarity Control

STANDBY (Pin)

STANDBYINV (SPI bit)

STANDBY Control(41)

Notes

41.

STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby

Table 30. Delay of STANDBY- Initiated Response

STBYDLY[1:0]

Function

No Delay

One 32 k period (default)

Two 32 k periods

Three 32 k periods

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