MC34708 datasheet(42/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

MC34708

Functional Block Description

7.5.3.7

Power Monitoring

The voltage at BATT and BP are monitored by detectors as summarized in Table 27.

The UVDET and LOWBATT thresholds are related to the power on/off events as described earlier in this chapter. The LOWBATT

threshold when transitioned from low to a high is used to power on the MC34708. The LOWBATT threshold when transitioned

from high to low, is used as a low battery detect warning. An interrupt LOWBAT is generated when dropping below the high to

low threshold to indicate to the processor that the battery is weak and a shutdown is imminent.

The LOWBATT detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 28.

7.5.3.8

Power Saving

7.5.3.8.1

System Standby

A product may be designed to go into DSM after periods of inactivity, the STANDBY pin is provided for board level control of

timing in and out of such deep sleep modes.

When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing

the operating mode of the switching regulators or disabling some regulators. This can be obtained by controlling the STANDBY

pin. The configuration of the regulators in standby is pre-programmed through the SPI.

A lower power standby mode can be obtained by setting the ON_STBY_LP SPI bit to a one. With the ON_STBY_LP SPI bit set

and the STANDBY pin asserted a lower power standby will be entered. In the on Standby Low Power mode, the switching

Regulators should all be programmed into PFM mode and the LDO's should be configured to Low Power mode when the

STANDBY pin is asserted. The PLL is disabled in this mode so the mini USB will only be able to detect if a charger is inserted.

If an audio device, UART, or a USB OTG device is attached the PMIC will not be able to auto detect it in Low Power Standby

Table 27. LOWBATT Detection Thresholds

Threshold in V

Bit setting(38)

UVDET (V)

L to H transition

(Power on)(39)

,(40)

H to L transition

(Low battery detect)(39)

,(40)

LOWBATT1

LOWBATT0

LOWBATT

3.1 (Rising)

2.65 (Falling)

3.1

3.0

3.1 (Rising)

2.65 (Falling)

3.2

3.1

3.1 (Rising)

2.65 (Falling)

3.3

3.2

3.1 (Rising)

2.65 (Falling)

3.4

3.3

Notes

38.

Default setting for LOWBATT[1:0] is 11.

39.

The above specified thresholds are ±50 mV accurate for the indicated transition

40.

A hysteresis is applied to the detectors on the order of 100 mV

Table 28. VBATTDB Debounce Times

VATTDB[1:0]

Debounce Time

0 (default)

2 RTC clock cycles

4 RTC clock cycles

8 RTC clock cycles

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