MCP795W21 datasheet(29/54 Pages) MAS

29 / 54 page

 2011 Microchip Technology Inc.

Preliminary

DS22280A-page 29

MCP795WXX/MCP795BXX

In the case where the MSB of the Calibration register

is set to ‘1’, the CLKOUT output waveforms that

appear when bits RS1 and RS0 are set to ‘01’ or ‘10’

are not as responsive to the setting of the Calibration

waveform (RS1, RS0 set to ‘01’), the output waveform

is generated using only eight input clock cycles.

Consequently, attempting to subtract more than eight

input clock cycles from this output does not have a

meaningful affect on the resulting waveform. Any

affect on the output will appear as a modification in

both the frequency and duty cycle of the waveform

appearing on the CLKOUT output pin.

B.RS2 bit set to ‘1’

With the RS2 bit set to ‘1’, the following internal timing

signal is output on the CLKOUT pin:

The frequency listed in the table presumes an input

clock source of exactly 32.768 kHz. In terms of the

equivalent number of input clock cycles, the table

becomes:

Unlike

the

method

previously

described,

the

calibration setting is continuously applied and affects

every cycle of the output waveform. This results in the

modulation of the frequency of the output waveform

based upon the setting of the Calibration register.

Using this setting, the calibration function can be

expressed as:

Since the calibration is done every cycle, the frequency

of the output CLKOUT waveform is constant.

FIGURE 9-1:

CLKOUT WAVEFORM

RS2

RS1

RS0

Output Signal

1.0 Hz

RS2

RS1

RS0

Output Signal

32768

Toutput

(32768 +/- (2 * CALREG)) Tinput

where:

Toutput

clock period of CLKOUT output

signal

Tinput

clock period of input signal

CALREG

decimal value of calibration

determined by the CALSGN bit.

Delay

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