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MCP795W21 数据表(PDF) 38 Page - Micro Analog systems |
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MCP795W21 数据表(HTML) 38 Page - Micro Analog systems |
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38 / 54 page  MCP795WXX/MCP795BXX DS22280A-page 38 Preliminary 2011 Microchip Technology Inc. 10.0 ON-BOARD MEMORY The MCP795XXX has both on-board EEPROM mem- ory and battery-backed SRAM. The SRAM is arranged as 64 x 8 bytes and is retained when VCC supply is removed. The EEPROM is organized as 256/128 x 8 bytes. The EEPROM is nonvolatile and does not require VBAT supply for retention. 10.1 SRAM The SRAM array is a battery-backed-up array of 64 bytes. The SRAM is accessed using the Read and Write commands, starting at address 0x20h. Upon power-up the SRAM locations are in an unde- fined state but can be set to a known value using the CLRRAM instruction (Figure 9-8). 10.1.1 SRAM/RTCC OPERATION The MCP795XXX contains a Real-Time Clock and Cal- endar. The RTCC registers and SRAM array are accessed using the same commands. The RTCC reg- isters and SRAM array are powered internally from the switched supply that is either connected to VCC or VBAT supply. No external read/write operations are permitted when the device is running from the VBAT supply. Table 1-2 contains a list of the possible instruction bytes and format for device operation. 10.1.2 READ SEQUENCE The part is selected by pulling CS low. The 8-bit READ instruction is transmitted to the MCP795W20 followed by the 8-bit address (A7 through A0). After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to pro- vide clock pulses. The internal Address Pointer is auto- matically incremented to the next higher address after each byte of data is shifted out. As the RTCC registers are separate from the SRAM array, when reading the RTCC registers set the address will wrap back to the start of the RTCC regis- ters. Also when an address within the SRAM array is loaded the internal Address Pointer will wrap back to the start of the SRAM array. The READ instruction can be used to read the registers and array indefinitely by continuing to clock the device. The read operation is terminated by raising the CS pin (Figure 10-1). 10.1.3 WRITE SEQUENCE As the RTCC registers and SRAM array do not require the WREN sequence like the nonvolatile memory, the user may proceed by setting the CS low, issuing the WRITE instruction, followed by the address, and then the data to be written. As no write cycle is required for the RTCC registers and SRAM array the entire con- tents can be written in a single command. For the last data byte to be written to the RTCC regis- ters and SRAM array, the CS must be brought high after the last byte has been clocked in. If CS is brought high at any other time, the last byte will not be written. Refer to Figure 10-2 for more detailed illustrations on the write sequence. FIGURE 10-1: READ SEQUENCE SO SI SCK CS 0 23456789 10 11 12 13 14 15 16 17 18 19 20 21 22 1 01 0 1 0 0 01 A7 6 5 4 1A0 76543210 Instruction Address Byte Data Out High-Impedance 23 32 Don’t Care The address will rollover to the start of either the RTCC registers or SRAM array. |
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