MCP795W21 datasheet(36/54 Pages) MAS

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MCP795WXX/MCP795BXX

DS22280A-page 36

Preliminary

 2011 Microchip Technology Inc.

9.1.10

DATA PROTECTION

The following protection has been implemented to pre-

vent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A Write Enable instruction must be issued to set

the write enable latch

• After a byte write, page write, unique ID write, or

STATUS register write, the write enable latch is

reset

•CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal EEPROM

write cycle is ignored and programming is contin-

ued

• Block protect bits are ignored for UID writes

9.1.11

CLEAR WATCHDOG INSTRUCTION

The Clear Watchdog command resets the internal

Watchdog Timer.

FIGURE 9-7:

CLRWDT

9.1.12

CLEAR RAM INSTRUCTION

The Clear Ram instruction is a 2-byte command that

will reset the internal SRAM to the known value. Using

this command, all locations in the SRAM are set to 00h

and the data value contained in the second byte of the

command is ignored.

FIGURE 9-8:

CLRRAM

SCK

High-Impedance

SCK

234567

89 10 11 12 13 14 15

A7 6

1A0

Instruction

Data

High-Impedance

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