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MCP795W21 数据表(PDF) 9 Page - Micro Analog systems |
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MCP795W21 数据表(HTML) 9 Page - Micro Analog systems |
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9 / 54 page  2011 Microchip Technology Inc. Preliminary DS22280A-page 9 MCP795WXX/MCP795BXX 3.2 Nonvolatile Memory Write Sequence Prior to any attempt to write data to the nonvolatile memory (EEPROM, Unique ID and STATUS register) in the MCP795XXX, the write enable latch must be set by issuing the EEWREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the MCP795XXX. After all eight bits of the instruction are transmitted, CS must be driven high to set the write enable latch. If the write operation is initiated immediately after the EEWREN instruction without CS driven high, data will not be writ- ten to the array since the write enable latch was not properly set. After setting the write enable latch, the user may pro- ceed by driving CS low, issuing either an EEWRITE, IDWRITE or a SWRITE instruction, followed by the remainder of the address, and then the data to be writ- ten. Up to 8 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Addi- tionally, a page address begins with XXXX 0000 and ends with XXXX X111. If the internal address counter reaches XXXX X111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and overwrite any data that previously existed in those locations. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is driven high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the non- volatile memory write is in progress, the STATUS reg- ister may be read to check the status of the WIP, WEL, BP1 and BP0 bits. Attempting to read a memory array location will not be possible during a write cycle. Polling the WIP bit in the STATUS register is recommended in order to determine if a write cycle is in progress. When the nonvolatile memory write cycle is completed, the write enable latch is reset. FIGURE 3-2: BYTE EEWRITE SEQUENCE FIGURE 3-3: PAGE EEWRITE SEQUENCE SO SI CS 0 23456789 10 11 1 00 0 0 0 0 01 A6 A5 A4 A1 A3 A2 Address Byte 12 13 14 15 16 17 18 19 20 21 22 23 Instruction Data Byte A0 6 7 5 43 2 1 0 High-Impedance Twc SCK A7 SI CS 910 11 00 0 0 0 0 01 765 432 10 Data Byte 1 SCK 0 2345 67 18 SI CS 33 34 35 38 39 7 65432 10 Data Byte n (8 max) SCK 24 26 27 28 29 30 31 25 32 7 6543 210 Data Byte 3 7 6543 210 Data Byte 2 36 37 Instruction Address Byte A7 A6 A5 A4 A3 A1 A0 A2 12 13 14 15 16 17 18 19 20 21 22 23 |
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