TNETE2008

OctalPHY

EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS042B – DECEMBER 1997 – REVISED JUNE 1998

5

POST OFFICE BOX 655303

Terminal Functions

controller interface – this block of signals is defined for each channel during its time slot (see

Figure 6)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

IFCLK

80

O

Interface clock. All ports handled by the interface use the same clock. The clock frequency is 20 MHz.

IFCOL

79

O

Collision. When asserted, IFCOL indicates a network collision on the current port.

IFCRS

78

O

Carrier sense. IFCRS indicates a frame carrier signal is being received on the current port. It asserts for

transmissions in half-duplex mode.

IFDUPLEX

83

O

Duplex mode. If IFDUPLEX is low, then the current port is in half duplex, otherwise it is full duplex. If the

IFFORCEHD signal is low, then IFDUPLEX also is low.

IFFORCEHD

90

I

Force half duplex. This terminal has two functions:

The first function concerns the values advertised during autonegotiation of link. If IFFORCEHD is low when

a channel latches in the control information about which modes it can advertise during autonegotiation (see

Figure 9), this channel is forced to half duplex. Values delivered on IFTXD0–IFTXD3 are overridden. If this

terminal is high at latch time, the modes are set by the values passed on IFTXD0–IFTXD3 during the period

before commencement of fast link pulse (FLP) exchange for this channel.

The second function is the ability of the terminal to drive link invalid for this channel during its time slot and

restart link validation. Link is driven invalid and reestablishing link starts when IFFORCEHD transitions from

one to zero or from zero to one; that is, any edge on IFFORCEHD drives link invalid and starts the process

of reestablishing link. Multiple edges in this signal before link is established force multiple restarts of the

linking process shown in Figure 9.

IFLINK

70

O

Interface link. IFLINK indicates the presence of port connection on the current port. Low is no link and high

is link made.

IFRXD3†

IFRXD2

IFRXD1

IFRXD0

72

73

74

75

O

Receive data. Receive data bits 3–0 from current port when IFRXDV is asserted. Receive data is clocked

out on falling edge of IFCLK.

IFSYNC

82

O

Interface sync. When IFSYNC is 1, the current port for MAC to TNETE2008 transfers is port 0. This signal

has a period of 400 ns and a duty cycle of 1:8. The port number for TNETE2008

→ MAC data is always two

slots ahead and is port 2 when IFSYNC is high. IFSYNC is sampled by the MAC on the falling edge of IFCLK.

IFTXD3†

IFTXD2

IFTXD1

IFTXD0

85

87

88

89

I

Transmit data bit. Transmit data bits 3–0 for the current port when IFTXEN is asserted. Data should change

on the rising edge of IFCLK to be clocked into the TNETE2008 on the following rising edge of IFCLK.

IFTXEN

84

I

Transmit enable. IFTXEN indicates that valid transmit data is on IFTXD0–IFTXD3.

IFRXDV

77

O

Receive data valid. This signal indicates the IFXRD0–IFXRD3 contain valid data.

† Most significant bit