TNETE2008

OctalPHY

EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS042B – DECEMBER 1997 – REVISED JUNE 1998

15

POST OFFICE BOX 655303

timing diagram

The basic signals on the multiplexed interface and their alignment to IFCLK and IFSYNC are shown in Figure 6.

All input signals change on the rising edge of IFCLK and are sampled by the TNETE2008 on the rising edge

of IFCLK. All output signals, except IFSYNC, change on the falling edge of IFCLK and should be sampled by

the MAC on the rising edge of IFCLK. The IFSYNC output changes on the rising edge of IFCLK and should be

sampled by the MAC on the falling edge of IFCLK.

IFSYNC

(output)

M00FHD

1

02

3

4

5

6

7

1

0

M00TXD

M00TXEN

M02COL

M02CRS

M02LINK

M02DUPLEX

M02RXD

M02RXDV

M01TXD

M01TXEN

M03COL

M03CRS

M03LINK

M03DUPLEX

M03RXD

M03RXDV

M02TXD

M02TXEN

M04COL

M04CRS

M04LINK

M04DUPLEX

M04RXD

M04RXDV

M03TXD

M03TXEN

M05COL

M05CRS

M05LINK

M05DUPLEX

M05RXD

M05RXDV

M04TXD

M04TXEN

M06COL

M06CRS

M06LINK

M06DUPLEX

M06RXD

M06RXDV

M05TXD

M06TXD

M07TXD

M00TXD

M01TXD

M05TXEN

M06TXEN

M07TXEN

M00TXEN

M01TXEN

M07COL

M07CRS

M07LNK

M07DUPLEX

M07RXD

M07RXDV

M00COL

M00CRS

M00LINK

M00DUPLEX

M00RXD

M00RXDV

M01COL

M01CRS

M01LINK

M01DUPLEX

M01RXD

M01RXDV

M02COL

M02CRS

M02LINK

M02DUPLEX

M02RXD

M02RXDV

M03COL

M03CRS

M03LINK

M03DUPLEX

M03RXD

M03RXDV

PORT

IFCLK

(output)

IFTXD3–

IFTXD0

(input)

IFTXEN

(input)

IFFORCEHD

(input)

IFCOL

(output)

IFCRS

(output)

IFLINK

(output)

IFDUPLEX

(output)

IFRXD3–

IFRXD0

(output)

IFRXDV

(output)

M01FHD

M02FHD

M03FHD

M04FHD

M05FHD

M06FHD

M07FHD

M00FHD

M01FHD

Note: Dashed line shows data from TNETE2008 to MAC is skewed by two slots.

Figure 6. MAC Interface