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TNETE2008 数据表(PDF) 14 Page - Texas Instruments

部件名 TNETE2008
功能描述  OctalPHY EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES
PDF  33 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETE2008 数据表(HTML) 14 Page - Texas Instruments

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TNETE2008
OctalPHY
EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES
SPWS042B – DECEMBER 1997 – REVISED JUNE 1998
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
synchronous PHY interface
To ease the pin-count burden on switching-application devices, Texas Instruments developed a multiplexed
interface, which allows multi-PHY devices to be connected to switching cores without using many terminals.
To achieve the reduction in terminal count, the interface takes advantage of the fact that modern silicon is able
to operate at frequencies much higher than the 10-MHz data rate of the standard interface.
The receive and transmit data are transferred over a nibble-wide bus, (see Figure 5). Table 1 describes the
signals on the interface. Any given port only transfers data at 2.5 MHz (2.5 MHz
× 4 bits = 10 Mbit/s). The
remaining control and status signals are sampled at the reduced rate of 2.5 MHz.
PHY
MAC
IFCLK
IFSYNC
IFCOL
IFCRS
IFLINK
IFDUPLEX
IFRXD3–IFRXD0
IFRXDV
IFTXD3–IFTXD0
IFTXEN
IFFORCEHD
CLK
SYNC
COL
CRS
LINK
DUPLEX
RXD3–RXD0
RXDV
TXD3–TXD0
TXEN
FORCEHD
Figure 5. Multiplexed 17-Pin Interface for Eight Ports
The interface runs synchronously to a TNETE2008 generated clock. The information (MAC
→ TNETE2008)
for the first port (port 0) is presented on the interface when IFSYNC is high; the next clock cycle the interface
carries the information for the second port. This process continues with each port using the interface for one
cycle. When all ports have been processed in this manner, the sequence resumes with the first port and again
IFSYNC is asserted. To improve latency-related issues, the data from the TNETE2008 to the MAC is skewed
by two slots as shown by the dashed line in Figure 6. This allows the MAC to respond to input signals from the
TNETE2008 in the same 400-ns cycle, rather than waiting for the next 400-ns cycle, which would be the case
if the signals were not skewed.
If the mode to be advertised during autonegotiation arrives on IFTXD3–IFTXD0 during link-invalid, IFFORCEHD
can be tied high or used to restart autonegotiation.



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