TNETE2008

OctalPHY

EIGHT 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS042B – DECEMBER 1997 – REVISED JUNE 1998

7

POST OFFICE BOX 655303

Terminal Functions (Continued)

miscellaneous interface

TERMINAL

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

AIREF

41

A

Current reference. Used to set a current reference for the analog circuitry. AIREF must be connected

to GND by a 2.5-k

Ω 1% resistor.

ARBIAS

37

A

Bias resistor for the analog circuitry. Connect 7.5-k

Ω 1% resistor between this pin and GND.

ATEST

39

A

Manufacturing test terminal. Leave unconnected.

CLK

43

I

Clock input. CLK connects a 20-MHz clock source to this terminal. The device enters a reset state on

loss of CLK.

LOOPBACK

47

I

Loopback. When low, LOOPBACK enables internal loopback in all eight PHYs. When asserted, data is

internally wrapped within each PHY and does not appear on the network. While in the looped-back state,

all network lines are placed in a noncontentious state.

MLT3BLOCK

69

I

MLT-3 block. Pulling MLT3 BLOCK terminal high enables the MLT-3 detector circuit and prevents the

TNETE2008 from asserting link or carrier sense in the presence of 100BASE-T data. Setting

MLT3BLOCK terminal low disables the MLT-3 detectors on all eight ports for applications that require

this.

RESET

46

I

Global reset. RESET is used to reset all eight PHY sections.

RCVTHRESH

44

I

Receive threshold. RCVTHRESH selects the threshold level of the receiver squelch circuit. For normal

IEEE Std 802.3 operation, this pin should be tied low. Setting RCVTHRESH high slightly lowers the

threshold level, allowing the PHY to receive data over extended lengths of cable for all eight PHYs.

PWRDOWN

45

I

Power down. When asserted, PWRDOWN places all eight PHYs in a low power state. Transmitting and

receiving are inhibited in this state.

† A = analog, I = input

not connected

TERMINAL

DESCRIPTION

NAME

NO.

DESCRIPTION

NC

31, 32, 33, 34, 35, 56, 57, 58, 59, 60,

91, 92, 93, 94, 116, 117, 118, 119, 120

No connection. No internal connection for these terminals.

power interface

TERMINAL

TYPE‡

DESCRIPTION

NAME

NO.

TYPE‡

DESCRIPTION

AGND

42

GND

Ground terminal for analog circuitry

AVDD

40

PWR

VDD terminal for analog circuitry. Connect to 3.3 V.

GND

55, 71, 81, 95, 96

GND

Logic ground terminals

RCVGND

109

GND

Ground terminal for receiver circuitry

RCVVDD

112

PWR

VDD terminals for receiver circuitry. Connect to 3.3 V.

XMTGND

3, 4, 7, 8, 11, 12,

15, 16, 19, 20, 23,

24, 27, 28, 36, 115

GND

Ground terminals for transmit circuitry

XMTVDD

38

PWR

VDD terminal for transmit circuitry. Connect to 3.3 V.

VCC

48

PWR

Power. Supply for JTAG port interface. Can be 5 V or 3.3 V, depending on test system interface

requirements.

VDD

50, 65, 76, 86

PWR

Logic VDD terminals. Connect these to 3.3 V.

‡ GND = ground, PWR = power