SST49LF040 datasheet(9/48 Pages) SST

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Advance Information

4 Mbit LPC Flash

SST49LF040

S71213-00-000

11/01 562

MODE SELECTION

The SST49LF040 flash memory devices can operate in

two distinct interface modes: the LPC mode and the Paral-

lel Programming (PP) mode. The mode pin is used to set

the interface mode selection. If the mode pin is set to logic

High, the device is in PP mode; while if the mode pin is set

Low, the device is in the LPC mode. The mode selection

pin must be configured prior to device operation. The mode

pin is internally pulled down if the pin is left unconnected. In

LPC mode, the device is configured to its host using stan-

dard LPC interface protocol. Communication between Host

and the SST49LF040 occurs via the 4-bit I/O communica-

tion signals, LAD [3:0] and LFRAME#. In PP mode, the

device is programmed via an 11-bit address and an 8-bit

data I/O parallel signals. The address inputs are multi-

plexed in row and column selected by control signal R/C#

pin. The row addresses are mapped to the higher internal

addresses, and the column addresses are mapped to the

lower internal addresses. See Figure 1, the Device Mem-

ory Map, for address assignments.

LPC MODE

CE#

The CE# pin, enables and disables the SST49LF040, con-

trolling Read and Write access of the device. To enable the

SST49LF040, the CE# pin must be driven low one clock

cycle prior to LFRAME# being driven low. CE# must

remain active low during internal Write (Erase or Program)

operations. The device will enter the Standby mode when

internal Write operations are completed and CE# is high.

LFRAME#

The LFRAME# signifies the start of a frame or the termina-

tion of a broken frame. Asserting LFRAME# for one or

more clock cycle and driving a valid START value on

LAD[3:0] will initiate device operation. The device will enter

the Standby mode when internal operations are completed

and LFRAME# is high.

Device Memory Hardware Write Protection

The Top Boot Lock (TBL#) and Write Protect (WP#) pins

are provided for hardware write protection of device mem-

ory in the SST49LF040. The TBL# pin is used to write pro-

tect 16 boot sectors (64 KByte) at the highest memory

address range for the SST49LF040. WP# pin write pro-

tects the remaining sectors in the flash memory.

An active low signal at the TBL# pin prevents Program and

Erase operations of the top boot sectors. When TBL# pin is

held high, the write protection of the top boot sectors is dis-

abled. The WP# pin serves the same function for the

remaining sectors of the device memory. The TBL# and

WP# pins write protection functions operate independently

of one another.

Both TBL# and WP# pins must be set to their required pro-

tection states prior to starting a Program or Erase opera-

tion. A logic level change occurring at the TBL# or WP# pin

during a Program or Erase operation could cause unpre-

dictable results.

Reset

A VIL on INIT# or RST# pin initiates a device reset. INIT#

and RST# pins have the same function internally. It is

required to drive INIT# or RST# pins low during a system

reset to ensure proper CPU initialization. During a Read

operation, driving INIT# or RST# pins low deselects the

device and places the output drivers, LAD[3:0], in a high-

impedance state. The reset signal must be held low for a

minimal duration of time TRSTP. A reset latency will occur if

a reset procedure is performed during a Program or Erase

operation. See Table 14, Reset Timing Parameters, for

more information. A device reset during an active Program

or Erase will abort the operation and memory contents may

become invalid due to data being altered or corrupted from

an incomplete Erase or Program operation.

Device Operation

The LPC mode uses a 5-signal communication interface, a

4-bit address/data bus, LAD[3:0], and a control line,

LFRAME#, to control operations of the SST49LF040.

Cycle type operations such as Memory Read and Memory

Write are defined in Intel Low Pin Count Interface Specifi-

cation, Revision 1.0. JEDEC Standard SDP (Software

Data

Protection)

Program

and

Erase

commands

sequences are incorporated into the standard LPC mem-

ory cycles. See Figure 12 through Figure 17 timing dia-

grams for command sequences.

LPC signals are transmitted via the 4-bit Address/Data bus

(LAD[3:0]), and follow a particular sequence, depending on

whether they are Read or Write operations. The standard

LPC memory cycle is defined in Table 18.

Both LPC Read and Write operations start in a similar way

as shown in Figures 10 and 11 timing diagrams. The host

(which is the term used here to describe the device driving

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