SST49LF040 datasheet(10/48 Pages) SST

10 / 48 page

Advance Information

4 Mbit LPC Flash

SST49LF040

S71213-00-000

11/01 562

the memory) asserts LFRAME# for one or more clocks

and drives a start value on the LAD[3:0] bus.

At the beginning of an operation, the host may hold the

LFRAME# active for several clock cycles, and even change

the Start value. The LAD[3:0] bus is latched every rising

edge of the clock. On the cycle in which LFRAME# goes

inactive, the last latched value is taken as the Start value.

CE# must be asserted one cycle before the start cycle to

select the SST49LF040 for Read and Write operations.

Once the SST49LF040 identifies the operation as valid (a

start value of all zeros), it next expects a nibble that indi-

cates whether this is a memory Read or Write cycle. Once

this is received, the device is now ready for the Address

and Data cycles. For Write operation the Data cycle will fol-

low the Address cycle, and for Read operation TAR and

SYNC cycles occur between the Address and Data cycles.

At the end of every operation, the control of the bus must

be returned to the host by a 2-clock TAR cycle.

Abort Mechanism

If LFRAME# is driven low for one or more clock cycles dur-

ing a LPC cycle, the cycle will be terminated and the device

will wait for the ABORT command. The host must drive the

LAD[3:0] with ‘1111b’ (ABORT command) to return the

device to the ready mode. If abort occurs during the inter-

nal write cycle, the data may be incorrectly programmed or

erased. It is required to wait for the Write operation to com-

plete prior to initiation of the abort command. It is recom-

mended to check the write status with Data# Polling D[7] or

Toggle Bit D[6]. One other option is to wait for the fixed write

time to expire.

Write Operation Status Detection

The SST49LF040 device provides two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to optimize the system write cycle time. The soft-

ware detection includes two status bits: Data# Polling D[7]

and Toggle Bit D[6]. The End-of-Write detection mode is

incorporated into the LPC Read Cycle. The actual comple-

tion of the nonvolatile write is asynchronous with the sys-

tem; therefore, either a Data# Polling or Toggle Bit read

may be simultaneous with the completion of the Write

cycle. If this occurs, the system may possibly get an errone-

ous result, i.e., valid data may appear to conflict with either

D[7] or D[6]. In order to prevent spurious rejection, if an

erroneous result occurs, the software routine should

include a loop to read the accessed location an additional

two (2) times. If both Reads are valid, then the device has

completed the Write cycle, otherwise the rejection is valid.

Data# Polling

When the SST49LF040 device is in the internal Program

operation, any attempt to read D[7] will produce the com-

plement of the true data. Once the Program operation is

completed, D[7] will produce true data. Note that even

though D[7] may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles. During internal Erase operation, any attempt to

read D[7] will produce a ‘0’. Once the internal Erase opera-

tion is completed, D[7] will produce a ‘1’. Proper status will

not be given using Data# Polling if the address is in the

invalid range.

Toggle Bit

During the internal Program or Erase operation, any consec-

utive attempts to read D[6] will produce alternating 0s and

1s, i.e., toggling between 0 and 1. When the internal Pro-

gram or Erase operation is completed, the toggling will stop.

System Memory Mapping

The LPC address sequence is 32 bits long. The

SST49LF040 will respond to addresses mapped into the

top of the 4GB memory space from FFFF FFFFH to

FF00 0000H or bottom of the 4GB memory space from

00000 000H to 00FF FFFFFH. Address bits A18-A0 are

decoded as memory addresses for SST49LF040, A22-A19

are device ID strapping bits, A23 directs Reads and Writes

to memory locations (A23 = 1) or to register access loca-

tions (A23 = 0).

Refer to Multiple Device Selection for more detail in device

ID strapping decoding. Refer to Figures 4 and 5 for System

Memory Boot Configuration.

Multiple Device Selection

Multiple LPC Flash devices may be strapped to increase

memory densities in a system. The four ID strapping pins,

ID[3:0], allow up to 16 devices to be attached to the same

bus by using different ID strapping in a system. Equal den-

sity must be used with multiple devices. BIOS support, bus

loading or the attaching bridge may limit this number. The

maximum “window” of the LPC array visible at one time is

16 MByte.

Applications that boot from the top address of the 4 GByte

system memory map; the ID strapping is sequentially

incremented downward as shown in Figure 4. For applica-

tions that boot from the bottom address of the 4 GByte sys-

tem memory map, the ID strapping increments upward but

non-sequentially as shown in Figure 5.

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