SST49LF040 datasheet(12/48 Pages) SST

12 / 48 page

Advance Information

4 Mbit LPC Flash

SST49LF040

S71213-00-000

11/01 562

FIGURE 5: BOOT CONFIGURATION FROM THE

BOTTOM OF THE 4 GBYTE SYSTEM

MEMORY MAP

Registers

There are two registers available on the SST49LF040, the

General Purpose Inputs Registers (GPI_REG) and the

JEDEC ID Registers. Since multiple LPC memory devices

may be used to increase memory densities, these registers

appear at its respective address location in the 4 GByte

system memory map. Unused register locations will read

as 00H. Any attempt to read registers during internal Write

operation will respond as “Write Operation Status Detec-

tion” (Data# Polling or Toggle Bit). Tables 4 and 5 list

GPI_REG

and

JEDEC

address

locations

for

SST49LF040 with its respective device strapping.

General Purpose Inputs Register

The GPI_REG (General Purpose Inputs Register) passes

the state of GPI[4:0] pins at power-up on the SST49LF040.

It is recommended that the GPI[4:0] pins be in the desired

state before LFRAME# is brought low for the beginning of

the next bus cycle, and remain in that state until the end of

the cycle. There is no default value since this is a pass-

through register. See Table 3, General Purpose Inputs

and 5 for memory address location for its respective device

strapping.

Device #14

Device #15

8 MByte

Memory Access

562 ILL F02.3

Device #2

Device #3

Device #1

Device #0

(Boot Block)

Device #14

Device #15

(Boot Block)

Device #3

Device #2

(Boot Block)

Device #1

Boot Device #0

00FF FFFFH

0080 0000H

007F FFFFH

0000 0000H

TABLE

3: GENERAL PURPOSE INPUTS REGISTER

Bit

Function

Pin #

32-PLCC

32-TSOP

7:5

Reserved

4GPI[4]

Reads status of general

purpose input pin

3GPI[3]

Reads status of general

purpose input pin

311

2GPI[2]

Reads status of general

purpose input pin

412

1GPI[1]

Reads status of general

purpose input pin

513

0GPI[0]

Reads status of general

purpose input pin

614

T3.1 562

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