SST49LF040 datasheet(14/48 Pages) SST

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Advance Information

4 Mbit LPC Flash

SST49LF040

S71213-00-000

11/01 562

PARALLEL PROGRAMMING MODE

Reset

Driving the RST# low will initiate a hardware reset of the

SST49LF040.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. The data portion of the software com-

mand sequence is latched on the rising edge of WE#.

During the software command sequence the row address

is latched on the falling edge of R/C# and the column

address is latched on the rising edge of R/C#.

Read

The Read operation of the SST49LF040 device is con-

trolled by OE#. OE# is the output control and is used to

gate data from the output pins. Refer to the Read cycle tim-

ing diagram, Figure 19, for further details.

Byte-Program Operation

The SST49LF040 device is programmed on a byte-by-byte

basis. Before programming, one must ensure that the sec-

tor in which the byte is programmed is fully erased. The

Byte-Program operation is initiated by executing a four-

byte-command load sequence for Software Data Protec-

tion with address (BA) and data in the last byte sequence.

During the Byte-Program operation, the row address (A10-

A0) is latched on the falling edge of R/C# and the column

address (A21-A11) is latched on the rising edge of R/C#.

The data bus is latched on the rising edge of WE#. The

Program operation, once initiated, will be completed, within

20 µs. See Figure 23 for Program operation timing diagram

and Figure 35 for its flowchart. During the Program opera-

tion, the only valid reads are Data# Polling and Toggle Bit.

During the internal Program operation, the host is free to

perform additional tasks. Any commands written during the

internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the

device on a sector-by-sector basis. The sector architecture

is based on uniform sector size of 4 KByte. The Sector-

Erase operation is initiated by executing a six-byte com-

mand load sequence for Software Data Protection with

Sector-Erase command (30H) and sector address (SA) in

the last bus cycle. The internal Erase operation begins after

the sixth WE# pulse. The End-of-Erase can be determined

using either Data# Polling or Toggle Bit methods. See Fig-

ure 24 for Sector-Erase timing waveforms. Any commands

written during the Sector-Erase operation will be ignored.

Block-Erase Operation

The Block-Erase Operation allows the system to erase the

device in 64 KByte uniform block size. The Block-Erase

operation is initiated by executing a six-byte command load

sequence for Software Data Protection with Block-Erase

command (50H) and block address. The internal Block-

Erase operation begins after the sixth WE# pulse. The

End-of-Erase can be determined using either Data# Polling

or Toggle Bit methods. See Figure 25 for Block-Erase tim-

ing waveforms. Any commands written during the Block-

Erase operation will be ignored.

Chip-Erase Operation

The SST49LF040 device provides a Chip-Erase operation,

which allows the user to erase the entire memory array to

the “1s” state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte Software Data Protection command sequence with

Chip-Erase command (10H) with address 5555H in the last

byte sequence. The internal Erase operation begins with

the rising edge of the sixth WE#. During the internal Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 8 for the command sequence, Figure 26 for

Chip-Erase timing diagram, and Figure 38 for the flowchart.

Any commands written during the Chip-Erase operation

will be ignored.

Write Operation Status Detection

The SST49LF040 device provides two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to optimize the system write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE# which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

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