ThunderLAN

™ TNETE110PM

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS029 – SEPTEMBER 1996

2

POST OFFICE BOX 1443

PCI

Bus

PCI

Bus Master

Control

FIFO

Registers

Multiplexed

SRAM

FIFO

Ethernet

LAN

Controller

10 Mbps

10 Base-T

Physical

Layer

Interface

10 Base-T

Ethernet

10 Base-5

(AUI)

Figure 1. ThunderLAN Architecture

description

ThunderLAN is a high-speed networking architecture that provides a complete PCI-to-10 Base-T/AUI Ethernet

solution. The TNETE110PM, one implementation of the ThunderLAN architecture (see Figure 1), is an

intelligent-protocol network interface. The ThunderLAN SRAM FIFO-based architecture eliminates the need for

external memory and offers a single-chip glueless PCI-to-10 Base-T/AUI (IEEE 802.3) solution with an on-board

physical layer interface.

The glueless PCI interface supports 32-bit streaming, operates at speeds up to 33 MHz, and is capable of

internal data-transfer rates up to 2 Gbps, taking full advantage of all available PCI bandwidth. The

TNETE110PM offers jumperless autoconfiguration using PCI configuration read / write cycles. Customizable

configuration registers, which can be autoloaded from an external serial EEPROM, allow designers of

TNETE110PM-based systems to give their systems a unique identification code. The TNETE110PM PCI

interface, developed in conjunction with other leaders in the semiconductor and computer industries, has been

vigorously tested on multiple platforms to ensure compatibility across a wide array of available PCI products.

In addition, the ThunderLAN drivers and ThunderLAN architecture use TI’s patented Adaptive Performance

Optimization (APO) technology to adjust critical parameters for minimum latency dynamically, minimum host

CPU utilization, and maximum system performance. This technology ensures that the maximum capabilities

of the PCI interface are used by automatically tuning the adapter to the specific system in which it is operating.

An intelligent protocol handler (PH) implements the serial protocols of the network. The PH is designed for

minimum overhead related to multiple protocols, using common state machines to implement 95% of the total

protocol handler. On transmit, the PH serializes data, adds framing and cyclic redundancy check (CRC) fields,

and interfaces to the network physical layer (PHY) chip. On receive, it provides address recognition, CRC and

error-checking, frame disassembly, and deserialization. Data for multiple channels is passed to and from the

PH by way of circular-buffer FIFOs in the FIFO SRAM.

Compliant with IEEE Standard 1149.1, the TNETE110PM provides a five-pin test-access port that is used for

boundary-scan testing.

The TNETE110PM is available in a 144-pin thin quad flat package (TQFP) and quad flat package (QFP).

differences between TNETE110A and TNETE110PM

The TNETE110PM implements additional power management features such as Magic Packet and PCI

specification 2.1 compatibility for low power/sleep mode, advanced configuration and power interface (ACPI).