ThunderLAN

™ TNETE110PM

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS029 – SEPTEMBER 1996

7

POST OFFICE BOX 1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

PCI INTERFACE (CONTINUED)

PIRDY

19

I/O

PCI initiator ready. PIRDY is driven by the active bus master to indicate that it is ready to complete the

current data phase of a transaction. A data phase is not completed until both PIRDY and PTRDY are

sampled asserted. When the TNETE110PM is a bus master, it uses PIRDY to align incoming data on

reads or outgoing data on writes with its internal RAM-access synchronization (maximum one cycle

at the beginning of burst). When the TNETE110PM is a bus slave, it extends the access appropriately

until both PIRDY and PTRDY are asserted.

PTRDY

20

I/O

PCI target ready. PTRDY is driven by the selected device (bus slave or target) to indicate that it is ready

to complete the current data phase of a transaction. A data phase is not completed until both PIRDY

and PTRDY are sampled asserted.

ThunderLAN uses PTRDY to ensure every direct I/O (DIO) operation is correctly interlocked.

PPAR

27

I/O

PCI parity. PPAR carries even parity across PAD[31:0] and PC / BE[3:0]. It is driven by the

TNETE110PM during all address and write cycles as a bus master and during all read cycles as a bus

slave.

PPERR

24

I/O

PCI parity error. PPERR indicates a data parity error on all PCI transactions except special cycles.

PREQ

134

I/O

PCI bus request. PREQ is asserted by the TNETE110PM to request control of the PCI bus. This is not

a shared signal.

PRST

129

I

PCI reset signal (power-down enable configuration). The PRST pin should be connected to a reset

signal (VAUXGOOD) by the auxiliary power supply. This pin resets the TNETE110PM on initial power

up only. When PRST is asserted low, the TNETE110PM performs the following internal functions:

–

Resets all TNETE110PM registers and state machines

–

Puts all PCI outputs and IEEE standard (JTAG) pins in high impedance state asynchronously

PCI reset signal (clock-run-enable configuration). The PRST pin should be connected to the PRST

signal for the system. When PRST is asserted low, the TNETE110PM performs the following internal

functions:

–

Resets all TNETE110PM registers and state machines

–

Puts all PCI outputs and IEEE standard (JTAG) pins in high impedance state asynchronously

PSERR

25

O/D

PCI system error. PSERR indicates parity errors, or special cycle data parity errors.

PSTOP

23

I/O

PCI stop. PSTOP indicates the current target is requesting the master to stop the current transaction.

BIOS ROM / LED DRIVER INTERFACE

EAD7

EAD6

EAD5

EAD4

EAD3

EAD2

EAD1

EAD0

54

55

56

57

59

60

61

62

I/O

EPROM address / data. EAD[7:0] is a multiplexed byte bus that is used to address and read data from

an external BIOS ROM.

• On the cycle when EXLE is asserted low, EAD[7:0] is driven with the high byte of the

address.

• On the cycle when EALE is asserted low, EAD[7:0] is driven with the low byte of the

address.

• When EOE is asserted, BIOS ROM data should be placed on the bus.

These pins can also be used to drive external status LEDs. Low-current (2 – 5 mA) LEDs can be

connected directly (through appropriate resistors). High-current LEDs can be driven through buffers

or from the BIOS ROM address latches.

EALE

65

O

EPROM address latch enable. EALE is driven low to latch the low (least significant) byte of the BIOS

ROM address from EAD[7:0].

EOE

64

O

EPROM output enable. When EOE is active (low) EAD[7:0] is in the high-impedance state and the

output of the BIOS ROM should be placed on EAD[7:0].

EXLE

66

O

EPROM extended address latch enable. EXLE is driven low to latch the high (most significant) byte

of the BIOS ROM address from EAD[7:0].

† I = input, O = output, I / O = 3-state input / output, O / D = open-drain output, A = analog

NOTE 1: This pin should be tied to VDD with a 4.7-kW – 10-kW pullup resistor.