ThunderLAN

™ TNETE110PM

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS029 – SEPTEMBER 1996

6

POST OFFICE BOX 1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

PCI INTERFACE (CONTINUED)

PAD7

42

PAD6

43

PAD5

45

PAD4

46

I/O

PCI address / data bus Byte 0 (least significant) of the PCI address / data bus

PAD3

47

I/O

PCI address / data bus. Byte 0 (least significant) of the PCI address / data bus

PAD2

49

PAD1

50

PAD0

51

PCLK

131

I

PCI clock. PCLK is the clock reference for all PCI bus operations. All other PCI pins except PRST and

PINTA are sampled on the rising edge of PCLK. All PCI bus timing parameters are defined with respect

to this edge.

PCLKRUN

53

I/O ‡

Clock run control (power-down-enable configuration). The PCLKRUN pin should be connected to the

PRST signal for the system. This reset is generated by the VDDI supply and, therefore, is used to put

the TNETE110PM into D3off mode when SOPD = 1. When the PCLKRUN pin is asserted low, the

TNETE110PM performs the following internal functions:

–

Disables PCLK during sleep state

–

Puts all PCI outputs in high-impedance mode asynchronously

–

Disables PFRAME to ensure that the TNETE110PM is signaled as though it is doing a PCI I/O

cycle

–

Resets all TNETE110PM internal state machines

–

Disables all interrupts

–

Sets PowerState = 11 b (only if SOPD = 1)

–

Stops the transmitter and receiver (destructive)

Note: Ten PCLK cycles are required for the TNETE110PM to terminate PCI operations and reset all

state machines after PCLKRUN goes low.

Clock run control (clock-run-enable configuration). The PCLKRUN pin should be connected to the

PCLKRUN signal of the system. PCLKRUN is the active-low PCI clock request/grant signal that allows

the TNETE110PM to indicate when an active PCI clock is required (this is an open drain).

PC / BE3

PC / BE2

PC / BE1

PC / BE0

2

16

28

41

I/O

PCI bus command and byte enables. PC / BE3 enables byte 3 (MSB) of the PC / BE pins.

PCI bus command and byte enables. PC / BE2 enables byte 2 of PCI address / data bus.

PCI bus command and byte enables. PC / BE1 enables byte 1 of PCI address / data bus.

PCI bus command and byte enables. PC / BE0 enables byte 0 of PCI address / data bus.

PDEVSEL

21

I/O

PCI device select. PDEVSEL indicates that the driving device has decoded one of its addresses as

the target of the current access. The TNETE110PM drives PDEVSEL when it decodes an access to

one of its registers. As a bus master, the TNETE110PM monitors PDEVSEL to detect accesses to

illegal memory addresses.

PFRAME

17

I/O

PCI cycle frame. PFRAME is driven by the active bus master to indicate the beginning and duration

of an access. PFRAME is asserted to indicate the start of a bus transaction and remains asserted

during the transaction, only being deasserted in the final data phase.

PGNT

132

I

PCI bus grant. PGNT is asserted by the system arbiter to indicate that the TNETE110PM has been

granted control of the PCI bus.

PIDSEL

4

I

PCI initialization device select. PIDSEL is the chip select for access to PCI configuration registers.

PINTA

128

O/D

PCI interrupt. PINTA is the interrupt request from the TNETE110PM. PCI interrupts are shared, so this

is an open-drain (wired-OR) output.

† I = input, I / O = 3-state input / output, O / D = open-drain output

‡ Open drain