ThunderLAN

™ TNETE110PM

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS029 – SEPTEMBER 1996

8

POST OFFICE BOX 1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

CONFIGURATION EEPROM INTERFACE

EDCLK

68

O

EEPROM data clock. EDCLK transfers serial clocked data to the 2K-bit serial EEPROMs (24C02) (see

Note 1).

EDIO

69

I/O

EEPROM data I / O. EDIO is the bidirectional serial data / address line to the 2K-bit serial EEPROM

(24C02). EDIO requires an external pullup for EEPROM operation. Tying EDIO to ground disables the

EEPROM interface and prevents autoconfiguration of the PCI configuration register.

NETWORK INTERFACE (10 Base-T AND AUI)

ACOLN

ACOLP

111

109

A

AUI-receive pair. ACOLN and ACOLP are differential line-receiver inputs and connect to receive pair

via transformer isolation, etc.

ARCVN

ARCVP

108

106

A

AUI-receive pair. ARCVN and ARCVP are differential line-receiver inputs and connect to receive pair

via transformer isolation, etc.

AXMTP

AXMTN

99

100

A

AUI-transmit pair. AXMTP and AXMTN are differential line-transmitter outputs.

FATEST

118

A

Analog test pin. FATEST provides access to the filter of the reference PLL. This pin should be left as

a no connect.

FIREF

116

A

Current reference. FIREF is used to set a current reference for the analog circuitry.

FONLY

120

A

Front-end only pin. The FONLY pin should be tied low for systems not requiring the power management

capabilities of the TNETE110PM.

FRCVN

FRCVP

105

103

A

10 Base-T receive pair. FRCVN and FRCVP are differential line receiver inputs and connect to receive

pair via transformer isolation, etc.

FXTL1

FXTL2

113

114

A

Crystal oscillator pins. Drive FXTL1 from a 20-MHz crystal oscillator module.

FXMTP

FXMTN

97

98

A

10 Base-T transmit pair. FXMTP and FXMTN are differential line transmitter outputs.

RESERVED

120

I

Reserved. Tie this pin low.

SERIAL MANAGEMENT INTERFACE

MDIO

93

I/O

Management data I/O. MDIO is part of the serial management interface.

MRCLK

82

I

Receive clock. MRCLK is the receive clock source.

MRST

95

O

MII reset. MRST is the reset signal.

POWER

VDDI

6, 14,

34, 48,

122,

136,

142

PWR

PCI VDD pins (power-down-enable configuration). VDDI pins provide power for the PCI I/O pin drivers.

Connect VDDI pins to a 5-volt power supply when using 5-V signals on the PCI bus. Connect VDDI pins

to a 3-volt power supply when using 3-V signals on the PCI bus. Pin #122 should be connected to a

power supply that is not powered down during SLEEP mode. This supply must be the same voltage

as VDDI when the PCI bus is fully functional.

PCI VDD pins (clock-run-enable configuration). VDDI pins provide power for the PCI I/O pin drivers.

Connect VDDI pins to a 5-volt power supply when using 5-V signals on the PCI bus. Connect VDDI pins

to a 3-volt power supply when using 3-V signals on the PCI bus.

VDDL

22, 37,

58, 70,

79, 84

94,

130

PWR

Logic VDD pins (5 V) (power-down-enable configuration). VDDL pins provide power for internal

TNETE110PM logic and should be connected to an auxiliary power source (5 V).

Logic VDD pins (5 V) (Clock-run-enable configuration). VDDL pins provide power for internal

TNETE110PM logic, and they always must be connected to 5 V.