ThunderLAN

™ TNETE110PM

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS029 – SEPTEMBER 1996

10

POST OFFICE BOX 1443

DMA controller (DMAC)

The DMAC is responsible for coordinating TNETE110PM requests for mastership of the PCI bus. The DMAC

provides byte-aligning DMA control allowing byte-size fragmented frames to be transferred to any byte address

while supporting 32-bit data streaming.

protocol handler (PH)

The PH implements the serial protocols of the network. On transmit, it serializes data, adds framing and CRC

fields, and interfaces to the network PHY. On receive, it provides address recognition, CRC and error checking,

frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of

circular buffer FIFOs in the FSRAM controlled through FPREGS.

10 Base-T physical layer (PHY)

The PHY acts as an on-chip front-end providing physical layer functions for 10 Base-5 (AUI), 10 Base 2, and

10 Base-T (twisted pair). The PHY provides Manchester encoding / decoding from smart squelch, jabber

detection, link pulse detection, autopolarity control, 10 Base-T transmission waveshaping, and antialiasing

filtering. Connection to the AUI drop cable for the 10 Base-T twisted pair is made via simple isolation

transformers (see Figure 2) and no external filter networks are required. Suitable external termination

components allow the use of either shielded or unshielded twisted-pair cable (150

W or 100 W). Some of the

key features of the on-chip PHY are listed as follow:

TNETE110PM

PCI

FXMTP

FXMTN

FRCVP

FRCVN

RJ-45

Figure 2. Schematic for 10 Base-T Network Interface Using TNETE110PM

FIFO pointer registers (FPREGS)

The FPREGS are used to implement circular buffer FIFOs in the SRAM. They are a collection of pointer and

counter registers used to maintain the FIFO operation. Both the PCIIF and PH use FPREGS to determine where

to read or write data in the SRAM and to determine how much data the FIFO contains.