ThunderLAN

™ TNETE110PM

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS029 – SEPTEMBER 1996

9

POST OFFICE BOX 1443

Pin Functions (Continued)

POWER (CONTINUED)

VDDR

104

107

PWR

Analog power pin. VDDR is the 5-V power for the receiver circuitry.

VDDT

96

PWR

Analog power pin. VDDT is the 5-V power for the transmitter circuitry.

VDDVCO

117

PWR

Analog power pin. VDDVCO is the 5-V power for the voltage controller oscillator (VCO) and filter input.

VDDOSC

115

PWR

Analog power pin. VDDOSC is the 5-V power for the crystal oscillator circuit.

VSSI

3, 10,

26, 31,

40, 52,

67, 88,

127,

139

PWR

PCI I / O ground pins

VSSL

18, 44,

63, 75,

92,

133

PWR

Logic ground pins

VSSOSC

112

PWR

Analog power pin. Ground for crystal oscillator circuit

VSSR

102

110

PWR

Analog power pin. Ground for receiver circuitry

VSST

101

PWR

Analog power pin. Ground for transmitter circuitry

VSSVCO

119

PWR

Analog power pin. Ground for VCO and filter input

† I = input, A = analog, PWR = power

architecture

The major blocks of the TNETE110PM include the PCI interface (PCIIF), protocol handler (PH), physical layer

(PHY), FIFO pointer registers (FPREGS), FIFO SRAM (FSRAM), and a test-access port (TAP). The

functionality of these blocks is described in the following sections.

PCI interface (PCIIF)

The TNETE110PM PCIIF contains a byte-aligning DMA controller that allows frames to be fragmented into any

byte length and transferred to any byte address while supporting 32-bit data streaming. For multipriority

networks it can provide multiple data channels, each with separate lists, commands, and status. Data for the

channels is passed to and from the PH by way of circular buffer FIFOs in the SRAM, controlled through FIFO

registers. The configuration EEPROM interface (CEI), BIOS ROM /LED driver interface (BRI), configuration and

I / O memory registers (CIOREGS), and DMA controller are subblocks of the PCIIF. The features of these

subblocks are as follows:

configuration EEPROM interface (CEI)

The CEI provides a means for autoconfiguration of the PCI configuration registers. Certain registers in the PCI

configuration space may be loaded using the CEI. Autoconfiguration allows builders of TNETE110PM-based

systems to customize the contents of these registers to identify their own system, rather than using the TI

defaults. The EEPROM is read at power up and can then be read from, and written to, under program control.

BIOS ROM / LED driver interface (BRI)

The BRI addresses and reads data from an external BIOS ROM via a multiplexed byte-wide bus. The ROM

address / data pins also can be multiplexed to drive external status LEDs.

configuration and I / O memory registers (CIOREGS)

The CIOREGS reside in the configuration space, which is 256 bytes in length. The first 64 bytes of the

configuration space is the header region, which is explicitly defined by the PCI standard.